xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml (revision 84943d6f38e936ac3b7a3947ca26eeb27a39f938) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SC7280 TLMM block
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
14
15properties:
16  compatible:
17    const: qcom,sc7280-pinctrl
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    description: Specifies the TLMM summary IRQ
24    maxItems: 1
25
26  interrupt-controller: true
27
28  '#interrupt-cells':
29    description:
30      Specifies the PIN numbers and Flags, as defined in defined in
31      include/dt-bindings/interrupt-controller/irq.h
32    const: 2
33
34  gpio-controller: true
35
36  '#gpio-cells':
37    description: Specifying the pin number and flags, as defined in
38      include/dt-bindings/gpio/gpio.h
39    const: 2
40
41  gpio-ranges:
42    maxItems: 1
43
44  gpio-reserved-ranges:
45    minItems: 1
46    maxItems: 88
47
48  gpio-line-names:
49    maxItems: 175
50
51  wakeup-parent: true
52
53patternProperties:
54  "-state$":
55    oneOf:
56      - $ref: "#/$defs/qcom-sc7280-tlmm-state"
57      - patternProperties:
58          "-pins$":
59            $ref: "#/$defs/qcom-sc7280-tlmm-state"
60        additionalProperties: false
61
62$defs:
63  qcom-sc7280-tlmm-state:
64    type: object
65    description:
66      Pinctrl node's client devices use subnodes for desired pin configuration.
67      Client device subnodes use below standard properties.
68    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
69    unevaluatedProperties: false
70
71    properties:
72      pins:
73        description:
74          List of gpio pins affected by the properties specified in this
75          subnode.
76        items:
77          oneOf:
78            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
79            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
80                      sdc2_cmd, sdc2_data, ufs_reset ]
81        minItems: 1
82        maxItems: 16
83
84      function:
85        description:
86          Specify the alternative function to be configured for the specified
87          pins.
88
89        enum: [ atest_char, atest_char0, atest_char1, atest_char2,
90                atest_char3, atest_usb0, atest_usb00, atest_usb01,
91                atest_usb02, atest_usb03, atest_usb1, atest_usb10,
92                atest_usb11, atest_usb12, atest_usb13, audio_ref,
93                cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
94                cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
95                cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
96                cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
97                dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
98                gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
99                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
100                mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
101                mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
102                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
103                mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
104                mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
105                mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
106                pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
107                pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
108                qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
109                qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
110                qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
111                qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
112                sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
113                sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
114                tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
115                uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
116                usb_phy, vfr_0, vfr_1, vsense_trigger ]
117
118    required:
119      - pins
120
121allOf:
122  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
123
124required:
125  - compatible
126  - reg
127  - interrupts
128  - interrupt-controller
129  - '#interrupt-cells'
130  - gpio-controller
131  - '#gpio-cells'
132  - gpio-ranges
133
134additionalProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139    tlmm: pinctrl@f000000 {
140        compatible = "qcom,sc7280-pinctrl";
141        reg = <0xf000000 0x1000000>;
142        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
143        gpio-controller;
144        #gpio-cells = <2>;
145        interrupt-controller;
146        #interrupt-cells = <2>;
147        gpio-ranges = <&tlmm 0 0 175>;
148        wakeup-parent = <&pdc>;
149
150        qup_uart5_default: qup-uart5-state {
151            pins = "gpio46", "gpio47";
152            function = "qup13";
153            drive-strength = <2>;
154            bias-disable;
155        };
156    };
157