xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8  Low Power Island (LPI) TLMM block
9
10maintainers:
11  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
13description: |
14  This binding describes the Top Level Mode Multiplexer block found in the
15  LPASS LPI IP on most Qualcomm SoCs
16
17properties:
18  compatible:
19    const: qcom,sc7280-lpass-lpi-pinctrl
20
21  qcom,adsp-bypass-mode:
22    description:
23      Tells ADSP is in bypass mode.
24    type: boolean
25
26  reg:
27    minItems: 2
28    maxItems: 2
29
30  gpio-controller: true
31
32  '#gpio-cells':
33    description: Specifying the pin number and flags, as defined in
34      include/dt-bindings/gpio/gpio.h
35    const: 2
36
37  gpio-ranges:
38    maxItems: 1
39
40#PIN CONFIGURATION NODES
41patternProperties:
42  '-pins$':
43    type: object
44    description:
45      Pinctrl node's client devices use subnodes for desired pin configuration.
46      Client device subnodes use below standard properties.
47    $ref: "/schemas/pinctrl/pincfg-node.yaml"
48
49    properties:
50      pins:
51        description:
52          List of gpio pins affected by the properties specified in this
53          subnode.
54        items:
55          oneOf:
56            - pattern: "^gpio([0-9]|[1-9][0-9])$"
57        minItems: 1
58        maxItems: 15
59
60      function:
61        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
62                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
63                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
64                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
65                dmic3_data, i2s2_data ]
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70      drive-strength:
71        enum: [2, 4, 6, 8, 10, 12, 14, 16]
72        default: 2
73        description:
74          Selects the drive strength for the specified pins, in mA.
75
76      slew-rate:
77        enum: [0, 1, 2, 3]
78        default: 0
79        description: |
80            0: No adjustments
81            1: Higher Slew rate (faster edges)
82            2: Lower Slew rate (slower edges)
83            3: Reserved (No adjustments)
84
85      bias-pull-down: true
86
87      bias-pull-up: true
88
89      bias-disable: true
90
91      output-high: true
92
93      output-low: true
94
95    required:
96      - pins
97      - function
98
99    additionalProperties: false
100
101required:
102  - compatible
103  - reg
104  - gpio-controller
105  - '#gpio-cells'
106  - gpio-ranges
107
108additionalProperties: false
109
110examples:
111  - |
112    lpass_tlmm: pinctrl@33c0000 {
113        compatible = "qcom,sc7280-lpass-lpi-pinctrl";
114        reg = <0x33c0000 0x20000>,
115              <0x3550000 0x10000>;
116        gpio-controller;
117        #gpio-cells = <2>;
118        gpio-ranges = <&lpass_tlmm 0 0 15>;
119    };
120