1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SA8775P TLMM block 8 9maintainers: 10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> 11 12description: | 13 Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sa8775p-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 "#gpio-cells": true 30 gpio-ranges: true 31 32 gpio-reserved-ranges: 33 minItems: 1 34 maxItems: 74 35 36 gpio-line-names: 37 maxItems: 148 38 39required: 40 - compatible 41 - reg 42 43additionalProperties: false 44 45patternProperties: 46 "-state$": 47 oneOf: 48 - $ref: "#/$defs/qcom-sa8775p-tlmm-state" 49 - patternProperties: 50 "-pins$": 51 $ref: "#/$defs/qcom-sa8775p-tlmm-state" 52 additionalProperties: false 53 54$defs: 55 qcom-sa8775p-tlmm-state: 56 type: object 57 description: 58 Pinctrl node's client devices use subnodes for desired pin configuration. 59 Client device subnodes use below standard properties. 60 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 61 unevaluatedProperties: false 62 63 properties: 64 pins: 65 description: 66 List of gpio pins affected by the properties specified in this 67 subnode. 68 items: 69 oneOf: 70 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$" 71 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ] 72 minItems: 1 73 maxItems: 16 74 75 function: 76 description: 77 Specify the alternative function to be configured for the specified 78 pins. 79 80 enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c, 81 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 82 cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, 83 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, 84 ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, 85 edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, 86 edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, 87 emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, 88 emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, 89 emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, 90 gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, 91 jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, 92 mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, 93 mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, 94 mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, 95 mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, 96 mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1, 97 pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk, 98 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, 99 qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, 100 qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, 101 qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, 102 qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0, 103 sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, 104 tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, 105 tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ] 106 107 required: 108 - pins 109 110examples: 111 - | 112 #include <dt-bindings/interrupt-controller/arm-gic.h> 113 114 tlmm: pinctrl@f000000 { 115 compatible = "qcom,sa8775p-tlmm"; 116 reg = <0xf000000 0x1000000>; 117 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 118 gpio-controller; 119 #gpio-cells = <2>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 gpio-ranges = <&tlmm 0 0 148>; 123 124 qup-uart10-state { 125 pins = "gpio46", "gpio47"; 126 function = "qup1_se3"; 127 }; 128 }; 129... 130