1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. QCM2290 TLMM block 8 9maintainers: 10 - Shawn Guo <shawn.guo@linaro.org> 11 12description: 13 This binding describes the Top Level Mode Multiplexer block found in the 14 QCM2290 platform. 15 16properties: 17 compatible: 18 const: qcom,qcm2290-tlmm 19 20 reg: 21 maxItems: 1 22 23 interrupts: 24 description: Specifies the TLMM summary IRQ 25 maxItems: 1 26 27 interrupt-controller: true 28 29 '#interrupt-cells': 30 description: 31 Specifies the PIN numbers and Flags, as defined in defined in 32 include/dt-bindings/interrupt-controller/irq.h 33 const: 2 34 35 gpio-controller: true 36 37 '#gpio-cells': 38 description: Specifying the pin number and flags, as defined in 39 include/dt-bindings/gpio/gpio.h 40 const: 2 41 42 gpio-ranges: 43 maxItems: 1 44 45 wakeup-parent: 46 maxItems: 1 47 48#PIN CONFIGURATION NODES 49patternProperties: 50 '-state$': 51 oneOf: 52 - $ref: "#/$defs/qcom-qcm2290-tlmm-state" 53 - patternProperties: 54 ".*": 55 $ref: "#/$defs/qcom-qcm2290-tlmm-state" 56 57'$defs': 58 qcom-qcm2290-tlmm-state: 59 type: object 60 description: 61 Pinctrl node's client devices use subnodes for desired pin configuration. 62 Client device subnodes use below standard properties. 63 $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" 64 65 properties: 66 pins: 67 description: 68 List of gpio pins affected by the properties specified in this 69 subnode. 70 items: 71 oneOf: 72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$" 73 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, 74 sdc2_clk, sdc2_cmd, sdc2_data ] 75 minItems: 1 76 maxItems: 36 77 78 function: 79 description: 80 Specify the alternative function to be configured for the specified 81 pins. 82 83 enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, 84 cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec, 85 cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist, 86 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, 87 gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, 88 jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, 89 mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1, 90 pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11, 91 pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist, 92 pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3, 93 pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio, 94 qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write, 95 ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, 96 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, 97 uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1, 98 vsense_trigger, wlan1_adc0, wlan1_adc1 ] 99 100 drive-strength: 101 enum: [2, 4, 6, 8, 10, 12, 14, 16] 102 default: 2 103 description: 104 Selects the drive strength for the specified pins, in mA. 105 106 bias-pull-down: true 107 108 bias-pull-up: true 109 110 bias-disable: true 111 112 output-high: true 113 114 output-low: true 115 116 required: 117 - pins 118 119 additionalProperties: false 120 121allOf: 122 - $ref: "pinctrl.yaml#" 123 124required: 125 - compatible 126 - reg 127 - interrupts 128 - interrupt-controller 129 - '#interrupt-cells' 130 - gpio-controller 131 - '#gpio-cells' 132 - gpio-ranges 133 134additionalProperties: false 135 136examples: 137 - | 138 #include <dt-bindings/interrupt-controller/arm-gic.h> 139 tlmm: pinctrl@500000 { 140 compatible = "qcom,qcm2290-tlmm"; 141 reg = <0x500000 0x300000>; 142 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 143 gpio-controller; 144 #gpio-cells = <2>; 145 interrupt-controller; 146 #interrupt-cells = <2>; 147 gpio-ranges = <&tlmm 0 0 127>; 148 149 sdc2_on_state: sdc2-on-state { 150 clk { 151 pins = "sdc2_clk"; 152 bias-disable; 153 drive-strength = <16>; 154 }; 155 156 cmd { 157 pins = "sdc2_cmd"; 158 bias-pull-up; 159 drive-strength = <10>; 160 }; 161 162 data { 163 pins = "sdc2_data"; 164 bias-pull-up; 165 drive-strength = <10>; 166 }; 167 }; 168 }; 169