1Qualcomm MSM8974 TLMM block 2 3Required properties: 4- compatible: "qcom,msm8974-pinctrl" 5- reg: Should be the base address and length of the TLMM block. 6- interrupts: Should be the parent IRQ of the TLMM block. 7- interrupt-controller: Marks the device node as an interrupt controller. 8- #interrupt-cells: Should be two. 9- gpio-controller: Marks the device node as a GPIO controller. 10- #gpio-cells : Should be two. 11 The first cell is the gpio pin number and the 12 second cell is used for optional parameters. 13- gpio-ranges: see ../gpio/gpio.txt 14 15Optional properties: 16 17- gpio-reserved-ranges: see ../gpio/gpio.txt 18 19Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 20a general description of GPIO and interrupt bindings. 21 22Please refer to pinctrl-bindings.txt in this directory for details of the 23common pinctrl bindings used by client devices, including the meaning of the 24phrase "pin configuration node". 25 26Qualcomm's pin configuration nodes act as a container for an arbitrary number of 27subnodes. Each of these subnodes represents some desired configuration for a 28pin, a group, or a list of pins or groups. This configuration can include the 29mux function to select on those pin(s)/group(s), and various pin configuration 30parameters, such as pull-up, drive strength, etc. 31 32The name of each subnode is not important; all subnodes should be enumerated 33and processed purely based on their content. 34 35Each subnode only affects those parameters that are explicitly listed. In 36other words, a subnode that lists a mux function but no pin configuration 37parameters implies no information about any pin configuration parameters. 38Similarly, a pin subnode that describes a pullup parameter implies no 39information about e.g. the mux function. 40 41 42The following generic properties as defined in pinctrl-bindings.txt are valid 43to specify in a pin configuration subnode: 44 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength. 45 46Non-empty subnodes must specify the 'pins' property. 47Note that not all properties are valid for all pins. 48 49 50Valid values for pins are: 51 gpio0-gpio145 52 Supports mux, bias and drive-strength 53 54 sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data 55 Supports bias and drive-strength 56 57 hsic_data, hsic_strobe 58 Supports only mux 59 60Valid values for function are: 61 cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, 62 blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, 63 blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2, 64 blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3, 65 blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4, 66 blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5, 67 blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, 68 blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7, 69 blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8, 70 blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9, 71 blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10, 72 blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, 73 blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12, 74 blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2 75 blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, 76 sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1, 77 cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2, 78 cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, 79 hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, 80 gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, 81 ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio 82 83 (Note that this is not yet the complete list of functions) 84 85 86 87Example: 88 89 msmgpio: pinctrl@fd510000 { 90 compatible = "qcom,msm8974-pinctrl"; 91 reg = <0xfd510000 0x4000>; 92 93 gpio-controller; 94 #gpio-cells = <2>; 95 gpio-ranges = <&msmgpio 0 0 146>; 96 interrupt-controller; 97 #interrupt-cells = <2>; 98 interrupts = <0 208 0>; 99 100 pinctrl-names = "default"; 101 pinctrl-0 = <&uart2_default>; 102 103 uart2_default: uart2_default { 104 mux { 105 pins = "gpio4", "gpio5"; 106 function = "blsp_uart2"; 107 }; 108 109 tx { 110 pins = "gpio4"; 111 drive-strength = <4>; 112 bias-disable; 113 }; 114 115 rx { 116 pins = "gpio5"; 117 drive-strength = <2>; 118 bias-pull-up; 119 }; 120 }; 121 }; 122