1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. MSM8953 TLMM block 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC. 14 15properties: 16 compatible: 17 const: qcom,msm8953-pinctrl 18 19 reg: 20 maxItems: 1 21 22 interrupts: true 23 interrupt-controller: true 24 "#interrupt-cells": true 25 gpio-controller: true 26 gpio-reserved-ranges: true 27 "#gpio-cells": true 28 gpio-ranges: true 29 30patternProperties: 31 "-state$": 32 oneOf: 33 - $ref: "#/$defs/qcom-msm8953-tlmm-state" 34 - patternProperties: 35 "-pins$": 36 $ref: "#/$defs/qcom-msm8953-tlmm-state" 37 additionalProperties: false 38 39$defs: 40 qcom-msm8953-tlmm-state: 41 type: object 42 description: 43 Pinctrl node's client devices use subnodes for desired pin configuration. 44 Client device subnodes use below standard properties. 45 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 46 47 properties: 48 pins: 49 description: 50 List of gpio pins affected by the properties specified in this 51 subnode. 52 items: 53 oneOf: 54 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" 55 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, 56 sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, 57 qdsd_data1, qdsd_data2, qdsd_data3 ] 58 minItems: 1 59 maxItems: 16 60 61 function: 62 description: 63 Specify the alternative function to be configured for the specified 64 pins. 65 66 enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, 67 atest_char, atest_char0, atest_char1, atest_char2, atest_char3, 68 atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens, 69 atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi, 70 blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, 71 blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, 72 blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, 73 blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo, 74 cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst, 75 cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c, 76 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 77 cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0, 78 cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11, 79 dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16, 80 dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20, 81 dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25, 82 dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7, 83 dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data, 84 ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a, 85 gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, 86 gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx, 87 gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot, 88 key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0, 89 lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, 90 mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync, 91 nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1, 92 pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b, 93 pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, 94 pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b, 95 pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0, 96 qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, 97 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, 98 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, 99 qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, 100 qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a, 101 sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout, 102 ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present, 103 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, 104 uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan, 105 wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ] 106 107 bias-pull-down: true 108 bias-pull-up: true 109 bias-disable: true 110 drive-strength: true 111 output-high: true 112 output-low: true 113 114 required: 115 - pins 116 117 additionalProperties: false 118 119allOf: 120 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 121 122required: 123 - compatible 124 - reg 125 126additionalProperties: false 127 128examples: 129 - | 130 #include <dt-bindings/interrupt-controller/arm-gic.h> 131 tlmm: pinctrl@1000000 { 132 compatible = "qcom,msm8953-pinctrl"; 133 reg = <0x01000000 0x300000>; 134 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 gpio-ranges = <&tlmm 0 0 142>; 140 141 serial_default: serial-state { 142 pins = "gpio4", "gpio5"; 143 function = "blsp_uart2"; 144 drive-strength = <2>; 145 bias-disable; 146 }; 147 }; 148