xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,msm8226-pinctrl.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MSM8226 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
14
15properties:
16  compatible:
17    const: qcom,msm8226-pinctrl
18
19  reg:
20    description: Specifies the base address and size of the TLMM register space
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31
32  gpio-reserved-ranges:
33    maxItems: 1
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-msm8226-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-msm8226-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-msm8226-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
61            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins. Functions are only valid for gpio pins.
69        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
70                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
71                blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
72                blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
73                gp0_clk, gp1_clk, sdc3, wlan ]
74
75    required:
76      - pins
77
78allOf:
79  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
80
81required:
82  - compatible
83  - reg
84
85additionalProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    msmgpio: pinctrl@fd510000 {
91        compatible = "qcom,msm8226-pinctrl";
92        reg = <0xfd510000 0x4000>;
93
94        gpio-controller;
95        #gpio-cells = <2>;
96        gpio-ranges = <&msmgpio 0 0 117>;
97        interrupt-controller;
98        #interrupt-cells = <2>;
99        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
100
101        serial-state {
102            pins = "gpio8", "gpio9";
103            function = "blsp_uart3";
104            drive-strength = <8>;
105            bias-disable;
106        };
107    };
108