xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml (revision 77013d11e6483b970af25e13c9b892075742f7e5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8  Low Power Island (LPI) TLMM block
9
10maintainers:
11  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
13description: |
14  This binding describes the Top Level Mode Multiplexer block found in the
15  LPASS LPI IP on most Qualcomm SoCs
16
17properties:
18  compatible:
19    const: qcom,sm8250-lpass-lpi-pinctrl
20
21  reg:
22    minItems: 2
23    maxItems: 2
24
25  clocks:
26    items:
27      - description: LPASS Core voting clock
28      - description: LPASS Audio voting clock
29
30  clock-names:
31    items:
32      - const: core
33      - const: audio
34
35  gpio-controller: true
36
37  '#gpio-cells':
38    description: Specifying the pin number and flags, as defined in
39      include/dt-bindings/gpio/gpio.h
40    const: 2
41
42  gpio-ranges:
43    maxItems: 1
44
45#PIN CONFIGURATION NODES
46patternProperties:
47  '-pins$':
48    type: object
49    description:
50      Pinctrl node's client devices use subnodes for desired pin configuration.
51      Client device subnodes use below standard properties.
52    $ref: "/schemas/pinctrl/pincfg-node.yaml"
53
54    properties:
55      pins:
56        description:
57          List of gpio pins affected by the properties specified in this
58          subnode.
59        items:
60          oneOf:
61            - pattern: "^gpio([0-9]|[1-9][0-9])$"
62        minItems: 1
63        maxItems: 14
64
65      function:
66        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
67                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
68                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
69                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
70                dmic3_data, i2s2_data ]
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75      drive-strength:
76        enum: [2, 4, 6, 8, 10, 12, 14, 16]
77        default: 2
78        description:
79          Selects the drive strength for the specified pins, in mA.
80
81      slew-rate:
82        enum: [0, 1, 2, 3]
83        default: 0
84        description: |
85            0: No adjustments
86            1: Higher Slew rate (faster edges)
87            2: Lower Slew rate (slower edges)
88            3: Reserved (No adjustments)
89
90      bias-pull-down: true
91
92      bias-pull-up: true
93
94      bias-disable: true
95
96      output-high: true
97
98      output-low: true
99
100    required:
101      - pins
102      - function
103
104    additionalProperties: false
105
106required:
107  - compatible
108  - reg
109  - clocks
110  - clock-names
111  - gpio-controller
112  - '#gpio-cells'
113  - gpio-ranges
114
115additionalProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/sound/qcom,q6afe.h>
120    lpi_tlmm: pinctrl@33c0000 {
121        compatible = "qcom,sm8250-lpass-lpi-pinctrl";
122        reg = <0x33c0000 0x20000>,
123              <0x3550000 0x10000>;
124        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
125                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
126        clock-names = "core", "audio";
127        gpio-controller;
128        #gpio-cells = <2>;
129        gpio-ranges = <&lpi_tlmm 0 0 14>;
130    };
131