xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
15
16properties:
17  compatible:
18    const: qcom,ipq9574-tlmm
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31  wakeup-parent: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 33
36
37  gpio-line-names:
38    maxItems: 65
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
44      - patternProperties:
45          "-pins$":
46            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
47        additionalProperties: false
48
49$defs:
50  qcom-ipq9574-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56    unevaluatedProperties: false
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
65        minItems: 1
66        maxItems: 8
67
68      function:
69        description:
70          Specify the alternative function to be configured for the specified
71          pins.
72
73        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
74                audio_pdm0, audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
75                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
76                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
77                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
78                cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
79                gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
80                pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake,
81                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm,
82                qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
83                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
84                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
85                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
86                qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
87                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
88                wci20, wci21, wsa_swrm ]
89
90    required:
91      - pins
92
93allOf:
94  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
95
96required:
97  - compatible
98  - reg
99
100additionalProperties: false
101
102examples:
103  - |
104    #include <dt-bindings/interrupt-controller/arm-gic.h>
105    tlmm: pinctrl@1000000 {
106        compatible = "qcom,ipq9574-tlmm";
107        reg = <0x01000000 0x300000>;
108        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
109        gpio-controller;
110        #gpio-cells = <2>;
111        interrupt-controller;
112        #interrupt-cells = <2>;
113        gpio-ranges = <&tlmm 0 0 65>;
114
115        uart2-state {
116            pins = "gpio34", "gpio35";
117            function = "blsp2_uart";
118            drive-strength = <8>;
119            bias-pull-down;
120        };
121    };
122