1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm IPQ5332 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 12 13description: | 14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. 15 16allOf: 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,ipq5332-tlmm 22 23 reg: 24 maxItems: 1 25 26 interrupts: 27 maxItems: 1 28 29 interrupt-controller: true 30 "#interrupt-cells": true 31 gpio-controller: true 32 "#gpio-cells": true 33 gpio-ranges: true 34 wakeup-parent: true 35 36 gpio-reserved-ranges: 37 minItems: 1 38 maxItems: 27 39 40 gpio-line-names: 41 maxItems: 53 42 43patternProperties: 44 "-state$": 45 oneOf: 46 - $ref: "#/$defs/qcom-ipq5332-tlmm-state" 47 - patternProperties: 48 "-pins$": 49 $ref: "#/$defs/qcom-ipq5332-tlmm-state" 50 additionalProperties: false 51 52$defs: 53 qcom-ipq5332-tlmm-state: 54 type: object 55 description: 56 Pinctrl node's client devices use subnodes for desired pin configuration. 57 Client device subnodes use below standard properties. 58 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 59 unevaluatedProperties: false 60 61 properties: 62 pins: 63 description: 64 List of gpio pins affected by the properties specified in this 65 subnode. 66 items: 67 pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$" 68 minItems: 1 69 maxItems: 36 70 71 function: 72 description: 73 Specify the alternative function to be configured for the specified 74 pins. 75 76 enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, 77 atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, 78 audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0, 79 blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, 80 blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, 81 blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0, 82 cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, 83 gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1, 84 mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, 85 pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1, 86 prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3, 87 qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, 88 qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, 89 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, 90 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, 91 qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, 92 qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0, 93 rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd, 94 wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ] 95 96 required: 97 - pins 98 99required: 100 - compatible 101 - reg 102 103additionalProperties: false 104 105examples: 106 - | 107 #include <dt-bindings/interrupt-controller/arm-gic.h> 108 109 tlmm: pinctrl@1000000 { 110 compatible = "qcom,ipq5332-tlmm"; 111 reg = <0x01000000 0x300000>; 112 gpio-controller; 113 #gpio-cells = <0x2>; 114 gpio-ranges = <&tlmm 0 0 53>; 115 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-controller; 117 #interrupt-cells = <0x2>; 118 119 serial0-state { 120 pins = "gpio18", "gpio19"; 121 function = "blsp0_uart0"; 122 drive-strength = <8>; 123 bias-pull-up; 124 }; 125 }; 126