1Qualcomm APQ8084 TLMM block 2 3This binding describes the Top Level Mode Multiplexer block found in the 4MSM8960 platform. 5 6- compatible: 7 Usage: required 8 Value type: <string> 9 Definition: must be "qcom,apq8084-pinctrl" 10 11- reg: 12 Usage: required 13 Value type: <prop-encoded-array> 14 Definition: the base address and size of the TLMM register space. 15 16- interrupts: 17 Usage: required 18 Value type: <prop-encoded-array> 19 Definition: should specify the TLMM summary IRQ. 20 21- interrupt-controller: 22 Usage: required 23 Value type: <none> 24 Definition: identifies this node as an interrupt controller 25 26- #interrupt-cells: 27 Usage: required 28 Value type: <u32> 29 Definition: must be 2. Specifying the pin number and flags, as defined 30 in <dt-bindings/interrupt-controller/irq.h> 31 32- gpio-controller: 33 Usage: required 34 Value type: <none> 35 Definition: identifies this node as a gpio controller 36 37- #gpio-cells: 38 Usage: required 39 Value type: <u32> 40 Definition: must be 2. Specifying the pin number and flags, as defined 41 in <dt-bindings/gpio/gpio.h> 42 43- gpio-ranges: 44 Usage: required 45 Definition: see ../gpio/gpio.txt 46 47- gpio-reserved-ranges: 48 Usage: optional 49 Definition: see ../gpio/gpio.txt 50 51Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 52a general description of GPIO and interrupt bindings. 53 54Please refer to pinctrl-bindings.txt in this directory for details of the 55common pinctrl bindings used by client devices, including the meaning of the 56phrase "pin configuration node". 57 58The pin configuration nodes act as a container for an arbitrary number of 59subnodes. Each of these subnodes represents some desired configuration for a 60pin, a group, or a list of pins or groups. This configuration can include the 61mux function to select on those pin(s)/group(s), and various pin configuration 62parameters, such as pull-up, drive strength, etc. 63 64 65PIN CONFIGURATION NODES: 66 67The name of each subnode is not important; all subnodes should be enumerated 68and processed purely based on their content. 69 70Each subnode only affects those parameters that are explicitly listed. In 71other words, a subnode that lists a mux function but no pin configuration 72parameters implies no information about any pin configuration parameters. 73Similarly, a pin subnode that describes a pullup parameter implies no 74information about e.g. the mux function. 75 76 77The following generic properties as defined in pinctrl-bindings.txt are valid 78to specify in a pin configuration subnode: 79 80- pins: 81 Usage: required 82 Value type: <string-array> 83 Definition: List of gpio pins affected by the properties specified in 84 this subnode. Valid pins are: 85 gpio0-gpio146, 86 sdc1_clk, 87 sdc1_cmd, 88 sdc1_data 89 sdc2_clk, 90 sdc2_cmd, 91 sdc2_data 92 93- function: 94 Usage: required 95 Value type: <string> 96 Definition: Specify the alternative function to be configured for the 97 specified pins. Functions are only valid for gpio pins. 98 Valid values are: 99 adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, 100 blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, 101 blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, 102 blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, 103 blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, 104 blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, 105 blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, 106 blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, 107 blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, 108 blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, 109 blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, 110 cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, 111 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 112 edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i 113 gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio, 114 hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic, 115 ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, 116 pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, 117 qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, 118 sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, 119 spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1, 120 tsif2, uim, uim_batt_alarm 121 122- bias-disable: 123 Usage: optional 124 Value type: <none> 125 Definition: The specified pins should be configured as no pull. 126 127- bias-pull-down: 128 Usage: optional 129 Value type: <none> 130 Definition: The specified pins should be configured as pull down. 131 132- bias-pull-up: 133 Usage: optional 134 Value type: <none> 135 Definition: The specified pins should be configured as pull up. 136 137- output-high: 138 Usage: optional 139 Value type: <none> 140 Definition: The specified pins are configured in output mode, driven 141 high. 142 Not valid for sdc pins. 143 144- output-low: 145 Usage: optional 146 Value type: <none> 147 Definition: The specified pins are configured in output mode, driven 148 low. 149 Not valid for sdc pins. 150 151- drive-strength: 152 Usage: optional 153 Value type: <u32> 154 Definition: Selects the drive strength for the specified pins, in mA. 155 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 156 157Example: 158 159 tlmm: pinctrl@fd510000 { 160 compatible = "qcom,apq8084-pinctrl"; 161 reg = <0xfd510000 0x4000>; 162 163 gpio-controller; 164 #gpio-cells = <2>; 165 gpio-ranges = <&tlmm 0 0 147>; 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 interrupts = <0 208 0>; 169 170 uart2: uart2-default { 171 mux { 172 pins = "gpio4", "gpio5"; 173 function = "blsp_uart2"; 174 }; 175 176 tx { 177 pins = "gpio4"; 178 drive-strength = <4>; 179 bias-disable; 180 }; 181 182 rx { 183 pins = "gpio5"; 184 drive-strength = <2>; 185 bias-pull-up; 186 }; 187 }; 188 }; 189