1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT8192 Pin Controller 8 9maintainers: 10 - Sean Wang <sean.wang@mediatek.com> 11 12description: | 13 The Mediatek's Pin controller is used to control SoC pins. 14 15properties: 16 compatible: 17 const: mediatek,mt8192-pinctrl 18 19 gpio-controller: true 20 21 '#gpio-cells': 22 description: | 23 Number of cells in GPIO specifier. Since the generic GPIO binding is used, 24 the amount of cells must be specified as 2. See the below 25 mentioned gpio binding representation for description of particular cells. 26 const: 2 27 28 gpio-ranges: 29 description: gpio valid number range. 30 maxItems: 1 31 32 gpio-line-names: true 33 34 reg: 35 description: | 36 Physical address base for gpio base registers. There are 11 GPIO 37 physical address base in mt8192. 38 maxItems: 11 39 40 reg-names: 41 description: | 42 Gpio base register names. 43 maxItems: 11 44 45 interrupt-controller: true 46 47 '#interrupt-cells': 48 const: 2 49 50 interrupts: 51 description: The interrupt outputs to sysirq. 52 maxItems: 1 53 54#PIN CONFIGURATION NODES 55patternProperties: 56 '-pins$': 57 type: object 58 additionalProperties: false 59 patternProperties: 60 '^pins': 61 type: object 62 description: | 63 A pinctrl node should contain at least one subnodes representing the 64 pinctrl groups available on the machine. Each subnode will list the 65 pins it needs, and how they should be configured, with regard to muxer 66 configuration, pullups, drive strength, input enable/disable and 67 input schmitt. 68 $ref: "pinmux-node.yaml" 69 70 properties: 71 pinmux: 72 description: | 73 Integer array, represents gpio pin number and mux setting. 74 Supported pin number and mux varies for different SoCs, and are defined 75 as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 76 77 drive-strength: 78 description: | 79 It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See 80 dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. 81 enum: [2, 4, 6, 8, 10, 12, 14, 16] 82 83 mediatek,drive-strength-adv: 84 description: | 85 Describe the specific driving setup property. 86 For I2C pins, the existing generic driving setup can only support 87 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they 88 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific 89 driving setup, the existing generic setup will be disabled. 90 The specific driving setup is controlled by E1E0EN. 91 When E1=0/E0=0, the strength is 0.125mA. 92 When E1=0/E0=1, the strength is 0.25mA. 93 When E1=1/E0=0, the strength is 0.5mA. 94 When E1=1/E0=1, the strength is 1mA. 95 EN is used to enable or disable the specific driving setup. 96 Valid arguments are described as below: 97 0: (E1, E0, EN) = (0, 0, 0) 98 1: (E1, E0, EN) = (0, 0, 1) 99 2: (E1, E0, EN) = (0, 1, 0) 100 3: (E1, E0, EN) = (0, 1, 1) 101 4: (E1, E0, EN) = (1, 0, 0) 102 5: (E1, E0, EN) = (1, 0, 1) 103 6: (E1, E0, EN) = (1, 1, 0) 104 7: (E1, E0, EN) = (1, 1, 1) 105 So the valid arguments are from 0 to 7. 106 $ref: /schemas/types.yaml#/definitions/uint32 107 enum: [0, 1, 2, 3, 4, 5, 6, 7] 108 109 mediatek,pull-up-adv: 110 description: | 111 Pull up settings for 2 pull resistors, R0 and R1. User can 112 configure those special pins. Valid arguments are described as below: 113 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 114 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 115 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 116 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 117 $ref: /schemas/types.yaml#/definitions/uint32 118 enum: [0, 1, 2, 3] 119 120 bias-pull-down: true 121 122 bias-pull-up: true 123 124 bias-disable: true 125 126 output-high: true 127 128 output-low: true 129 130 input-enable: true 131 132 input-disable: true 133 134 input-schmitt-enable: true 135 136 input-schmitt-disable: true 137 138 required: 139 - pinmux 140 141 additionalProperties: false 142 143allOf: 144 - $ref: "pinctrl.yaml#" 145 146required: 147 - compatible 148 - reg 149 - interrupts 150 - interrupt-controller 151 - '#interrupt-cells' 152 - gpio-controller 153 - '#gpio-cells' 154 - gpio-ranges 155 156additionalProperties: false 157 158examples: 159 - | 160 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 161 #include <dt-bindings/interrupt-controller/arm-gic.h> 162 pio: pinctrl@10005000 { 163 compatible = "mediatek,mt8192-pinctrl"; 164 reg = <0x10005000 0x1000>, 165 <0x11c20000 0x1000>, 166 <0x11d10000 0x1000>, 167 <0x11d30000 0x1000>, 168 <0x11d40000 0x1000>, 169 <0x11e20000 0x1000>, 170 <0x11e70000 0x1000>, 171 <0x11ea0000 0x1000>, 172 <0x11f20000 0x1000>, 173 <0x11f30000 0x1000>, 174 <0x1000b000 0x1000>; 175 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 176 "iocfg_bl", "iocfg_br", "iocfg_lm", 177 "iocfg_lb", "iocfg_rt", "iocfg_lt", 178 "iocfg_tl", "eint"; 179 gpio-controller; 180 #gpio-cells = <2>; 181 gpio-ranges = <&pio 0 0 220>; 182 interrupt-controller; 183 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 184 #interrupt-cells = <2>; 185 186 spi1-default-pins { 187 pins-cs-mosi-clk { 188 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 189 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 190 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 191 bias-disable; 192 }; 193 194 pins-miso { 195 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 196 bias-pull-down; 197 }; 198 }; 199 }; 200