xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/pinctrl-mt8192.yaml (revision 18054d0220cfc8df9c9568c437bd6fbb59d53c3c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT8192 Pin Controller
8
9maintainers:
10  - Sean Wang <sean.wang@mediatek.com>
11
12description: |
13  The Mediatek's Pin controller is used to control SoC pins.
14
15properties:
16  compatible:
17    const: mediatek,mt8192-pinctrl
18
19  gpio-controller: true
20
21  '#gpio-cells':
22    description: |
23      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
24      the amount of cells must be specified as 2. See the below
25      mentioned gpio binding representation for description of particular cells.
26    const: 2
27
28  gpio-ranges:
29    description: gpio valid number range.
30    maxItems: 1
31
32  reg:
33    description: |
34      Physical address base for gpio base registers. There are 11 GPIO
35      physical address base in mt8192.
36    maxItems: 11
37
38  reg-names:
39    description: |
40      Gpio base register names.
41    maxItems: 11
42
43  interrupt-controller: true
44
45  '#interrupt-cells':
46    const: 2
47
48  interrupts:
49    description: The interrupt outputs to sysirq.
50    maxItems: 1
51
52#PIN CONFIGURATION NODES
53patternProperties:
54  '^pins':
55    type: object
56    description: |
57      A pinctrl node should contain at least one subnodes representing the
58      pinctrl groups available on the machine. Each subnode will list the
59      pins it needs, and how they should be configured, with regard to muxer
60      configuration, pullups, drive strength, input enable/disable and
61      input schmitt.
62      An example of using macro:
63      pincontroller {
64        /* GPIO0 set as multifunction GPIO0 */
65        state_0_node_a {
66          pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
67        };
68        /* GPIO1 set as multifunction PWM */
69        state_0_node_b {
70          pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
71        };
72      };
73    $ref: "pinmux-node.yaml"
74
75    properties:
76      pinmux:
77        description: |
78          Integer array, represents gpio pin number and mux setting.
79          Supported pin number and mux varies for different SoCs, and are defined
80          as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
81
82      drive-strength:
83        description: |
84          It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
85          dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
86        enum: [2, 4, 6, 8, 10, 12, 14, 16]
87
88      bias-pull-down: true
89
90      bias-pull-up: true
91
92      bias-disable: true
93
94      output-high: true
95
96      output-low: true
97
98      input-enable: true
99
100      input-disable: true
101
102      input-schmitt-enable: true
103
104      input-schmitt-disable: true
105
106    required:
107      - pinmux
108
109    additionalProperties: false
110
111required:
112  - compatible
113  - reg
114  - interrupts
115  - interrupt-controller
116  - '#interrupt-cells'
117  - gpio-controller
118  - '#gpio-cells'
119  - gpio-ranges
120
121additionalProperties: false
122
123examples:
124  - |
125            #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
126            #include <dt-bindings/interrupt-controller/arm-gic.h>
127            pio: pinctrl@10005000 {
128                    compatible = "mediatek,mt8192-pinctrl";
129                    reg = <0x10005000 0x1000>,
130                          <0x11c20000 0x1000>,
131                          <0x11d10000 0x1000>,
132                          <0x11d30000 0x1000>,
133                          <0x11d40000 0x1000>,
134                          <0x11e20000 0x1000>,
135                          <0x11e70000 0x1000>,
136                          <0x11ea0000 0x1000>,
137                          <0x11f20000 0x1000>,
138                          <0x11f30000 0x1000>,
139                          <0x1000b000 0x1000>;
140                    reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
141                          "iocfg_bl", "iocfg_br", "iocfg_lm",
142                          "iocfg_lb", "iocfg_rt", "iocfg_lt",
143                          "iocfg_tl", "eint";
144                    gpio-controller;
145                    #gpio-cells = <2>;
146                    gpio-ranges = <&pio 0 0 220>;
147                    interrupt-controller;
148                    interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
149                    #interrupt-cells = <2>;
150
151                    pins {
152                      pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
153                      output-low;
154                    };
155            };
156