1* Mediatek MT8183 Pin Controller 2 3The Mediatek's Pin controller is used to control SoC pins. 4 5Required properties: 6- compatible: value should be one of the following. 7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl. 8- gpio-controller : Marks the device node as a gpio controller. 9- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 10 binding is used, the amount of cells must be specified as 2. See the below 11 mentioned gpio binding representation for description of particular cells. 12- gpio-ranges : gpio valid number range. 13- reg: physical address base for gpio base registers. There are 10 GPIO 14 physical address base in mt8183. 15 16Optional properties: 17- reg-names: gpio base register names. There are 10 gpio base register 18 names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", 19 "iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint". 20- interrupt-controller: Marks the device node as an interrupt controller 21- #interrupt-cells: Should be two. 22- interrupts : The interrupt outputs to sysirq. 23 24Please refer to pinctrl-bindings.txt in this directory for details of the 25common pinctrl bindings used by client devices. 26 27Subnode format 28A pinctrl node should contain at least one subnodes representing the 29pinctrl groups available on the machine. Each subnode will list the 30pins it needs, and how they should be configured, with regard to muxer 31configuration, pullups, drive strength, input enable/disable and input schmitt. 32 33 node { 34 pinmux = <PIN_NUMBER_PINMUX>; 35 GENERIC_PINCONFIG; 36 }; 37 38Required properties: 39- pinmux: integer array, represents gpio pin number and mux setting. 40 Supported pin number and mux varies for different SoCs, and are defined 41 as macros in boot/dts/<soc>-pinfunc.h directly. 42 43Optional properties: 44- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, 45 bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, 46 output-high, input-schmitt-enable, input-schmitt-disable 47 and drive-strength are valid. 48 49 Some special pins have extra pull up strength, there are R0 and R1 pull-up 50 resistors available, but for user, it's only need to set R1R0 as 00, 01, 51 10 or 11. So It needs config "mediatek,pull-up-adv" or 52 "mediatek,pull-down-adv" to support arguments for those special pins. 53 Valid arguments are from 0 to 3. 54 55 mediatek,tdsel: An integer describing the steps for output level shifter 56 duty cycle when asserted (high pulse width adjustment). Valid arguments 57 are from 0 to 15. 58 mediatek,rdsel: An integer describing the steps for input level shifter 59 duty cycle when asserted (high pulse width adjustment). Valid arguments 60 are from 0 to 63. 61 62 When config drive-strength, it can support some arguments, such as 63 MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. 64 It can only support 2/4/6/8/10/12/14/16mA in mt8183. 65 For I2C pins, there are existing generic driving setup and the specific 66 driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving 67 adjustment in generic driving setup. But in specific driving setup, 68 they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific 69 driving setup for I2C pins, the existing generic driving setup will be 70 disabled. For some special features, we need the I2C pins specific 71 driving setup. The specific driving setup is controlled by E1E0EN. 72 So we need add extra vendor driving preperty instead of 73 the generic driving property. 74 We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific 75 driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1. 76 It is used to enable or disable the specific driving setup. 77 E1E0 is used to describe the detail strength specification of the I2C pin. 78 When E1=0/E0=0, the strength is 0.125mA. 79 When E1=0/E0=1, the strength is 0.25mA. 80 When E1=1/E0=0, the strength is 0.5mA. 81 When E1=1/E0=1, the strength is 1mA. 82 So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. 83 84Examples: 85 86#include "mt8183-pinfunc.h" 87 88... 89{ 90 pio: pinctrl@10005000 { 91 compatible = "mediatek,mt8183-pinctrl"; 92 reg = <0 0x10005000 0 0x1000>, 93 <0 0x11f20000 0 0x1000>, 94 <0 0x11e80000 0 0x1000>, 95 <0 0x11e70000 0 0x1000>, 96 <0 0x11e90000 0 0x1000>, 97 <0 0x11d30000 0 0x1000>, 98 <0 0x11d20000 0 0x1000>, 99 <0 0x11c50000 0 0x1000>, 100 <0 0x11f30000 0 0x1000>, 101 <0 0x1000b000 0 0x1000>; 102 reg-names = "iocfg0", "iocfg1", "iocfg2", 103 "iocfg3", "iocfg4", "iocfg5", 104 "iocfg6", "iocfg7", "iocfg8", 105 "eint"; 106 gpio-controller; 107 #gpio-cells = <2>; 108 gpio-ranges = <&pio 0 0 192>; 109 interrupt-controller; 110 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 111 #interrupt-cells = <2>; 112 113 i2c0_pins_a: i2c0 { 114 pins1 { 115 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 116 <PINMUX_GPIO49__FUNC_SDA5>; 117 mediatek,pull-up-adv = <3>; 118 mediatek,drive-strength-adv = <7>; 119 }; 120 }; 121 122 i2c1_pins_a: i2c1 { 123 pins { 124 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 125 <PINMUX_GPIO51__FUNC_SDA3>; 126 mediatek,pull-down-adv = <2>; 127 mediatek,drive-strength-adv = <4>; 128 }; 129 }; 130 ... 131 }; 132}; 133