1== MediaTek MT7622 pinctrl controller == 2 3Required properties for the root node: 4 - compatible: Should be one of the following 5 "mediatek,mt7622-pinctrl" for MT7622 SoC 6 "mediatek,mt7629-pinctrl" for MT7629 SoC 7 - reg: offset and length of the pinctrl space 8 9 - gpio-controller: Marks the device node as a GPIO controller. 10 - #gpio-cells: Should be two. The first cell is the pin number and the 11 second is the GPIO flags. 12 13Optional properties: 14- interrupt-controller : Marks the device node as an interrupt controller 15 16If the property interrupt-controller is defined, following property is required 17- reg-names: A string describing the "reg" entries. Must contain "eint". 18- interrupts : The interrupt output from the controller. 19- #interrupt-cells: Should be two. 20 21Please refer to pinctrl-bindings.txt in this directory for details of the 22common pinctrl bindings used by client devices, including the meaning of the 23phrase "pin configuration node". 24 25MT7622 pin configuration nodes act as a container for an arbitrary number of 26subnodes. Each of these subnodes represents some desired configuration for a 27pin, a group, or a list of pins or groups. This configuration can include the 28mux function to select on those pin(s)/group(s), and various pin configuration 29parameters, such as pull-up, slew rate, etc. 30 31We support 2 types of configuration nodes. Those nodes can be either pinmux 32nodes or pinconf nodes. Each configuration node can consist of multiple nodes 33describing the pinmux and pinconf options. 34 35The name of each subnode doesn't matter as long as it is unique; all subnodes 36should be enumerated and processed purely based on their content. 37 38== pinmux nodes content == 39 40The following generic properties as defined in pinctrl-bindings.txt are valid 41to specify in a pinmux subnode: 42 43Required properties are: 44 - groups: An array of strings. Each string contains the name of a group. 45 Valid values for these names are listed below. 46 - function: A string containing the name of the function to mux to the 47 group. Valid values for function names are listed below. 48 49== pinconf nodes content == 50 51The following generic properties as defined in pinctrl-bindings.txt are valid 52to specify in a pinconf subnode: 53 54Required properties are: 55 - pins: An array of strings. Each string contains the name of a pin. 56 Valid values for these names are listed below. 57 - groups: An array of strings. Each string contains the name of a group. 58 Valid values for these names are listed below. 59 60Optional properies are: 61 bias-disable, bias-pull, bias-pull-down, input-enable, 62 input-schmitt-enable, input-schmitt-disable, output-enable 63 output-low, output-high, drive-strength, slew-rate 64 65 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for 66 slower slew rate respectively. 67 Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA. 68 69The following specific properties as defined are valid to specify in a pinconf 70subnode: 71 72Optional properties are: 73 - mediatek,tdsel: An integer describing the steps for output level shifter duty 74 cycle when asserted (high pulse width adjustment). Valid arguments are from 0 75 to 15. 76 - mediatek,rdsel: An integer describing the steps for input level shifter duty 77 cycle when asserted (high pulse width adjustment). Valid arguments are from 0 78 to 63. 79 80== Valid values for pins, function and groups on MT7622 == 81 82Valid values for pins are: 83pins can be referenced via the pin names as the below table shown and the 84related physical number is also put ahead of those names which helps cross 85references to pins between groups to know whether pins assignment conflict 86happens among devices try to acquire those available pins. 87 88 Pin #: Valid values for pins 89 ----------------------------- 90 PIN 0: "GPIO_A" 91 PIN 1: "I2S1_IN" 92 PIN 2: "I2S1_OUT" 93 PIN 3: "I2S_BCLK" 94 PIN 4: "I2S_WS" 95 PIN 5: "I2S_MCLK" 96 PIN 6: "TXD0" 97 PIN 7: "RXD0" 98 PIN 8: "SPI_WP" 99 PIN 9: "SPI_HOLD" 100 PIN 10: "SPI_CLK" 101 PIN 11: "SPI_MOSI" 102 PIN 12: "SPI_MISO" 103 PIN 13: "SPI_CS" 104 PIN 14: "I2C_SDA" 105 PIN 15: "I2C_SCL" 106 PIN 16: "I2S2_IN" 107 PIN 17: "I2S3_IN" 108 PIN 18: "I2S4_IN" 109 PIN 19: "I2S2_OUT" 110 PIN 20: "I2S3_OUT" 111 PIN 21: "I2S4_OUT" 112 PIN 22: "GPIO_B" 113 PIN 23: "MDC" 114 PIN 24: "MDIO" 115 PIN 25: "G2_TXD0" 116 PIN 26: "G2_TXD1" 117 PIN 27: "G2_TXD2" 118 PIN 28: "G2_TXD3" 119 PIN 29: "G2_TXEN" 120 PIN 30: "G2_TXC" 121 PIN 31: "G2_RXD0" 122 PIN 32: "G2_RXD1" 123 PIN 33: "G2_RXD2" 124 PIN 34: "G2_RXD3" 125 PIN 35: "G2_RXDV" 126 PIN 36: "G2_RXC" 127 PIN 37: "NCEB" 128 PIN 38: "NWEB" 129 PIN 39: "NREB" 130 PIN 40: "NDL4" 131 PIN 41: "NDL5" 132 PIN 42: "NDL6" 133 PIN 43: "NDL7" 134 PIN 44: "NRB" 135 PIN 45: "NCLE" 136 PIN 46: "NALE" 137 PIN 47: "NDL0" 138 PIN 48: "NDL1" 139 PIN 49: "NDL2" 140 PIN 50: "NDL3" 141 PIN 51: "MDI_TP_P0" 142 PIN 52: "MDI_TN_P0" 143 PIN 53: "MDI_RP_P0" 144 PIN 54: "MDI_RN_P0" 145 PIN 55: "MDI_TP_P1" 146 PIN 56: "MDI_TN_P1" 147 PIN 57: "MDI_RP_P1" 148 PIN 58: "MDI_RN_P1" 149 PIN 59: "MDI_RP_P2" 150 PIN 60: "MDI_RN_P2" 151 PIN 61: "MDI_TP_P2" 152 PIN 62: "MDI_TN_P2" 153 PIN 63: "MDI_TP_P3" 154 PIN 64: "MDI_TN_P3" 155 PIN 65: "MDI_RP_P3" 156 PIN 66: "MDI_RN_P3" 157 PIN 67: "MDI_RP_P4" 158 PIN 68: "MDI_RN_P4" 159 PIN 69: "MDI_TP_P4" 160 PIN 70: "MDI_TN_P4" 161 PIN 71: "PMIC_SCL" 162 PIN 72: "PMIC_SDA" 163 PIN 73: "SPIC1_CLK" 164 PIN 74: "SPIC1_MOSI" 165 PIN 75: "SPIC1_MISO" 166 PIN 76: "SPIC1_CS" 167 PIN 77: "GPIO_D" 168 PIN 78: "WATCHDOG" 169 PIN 79: "RTS3_N" 170 PIN 80: "CTS3_N" 171 PIN 81: "TXD3" 172 PIN 82: "RXD3" 173 PIN 83: "PERST0_N" 174 PIN 84: "PERST1_N" 175 PIN 85: "WLED_N" 176 PIN 86: "EPHY_LED0_N" 177 PIN 87: "AUXIN0" 178 PIN 88: "AUXIN1" 179 PIN 89: "AUXIN2" 180 PIN 90: "AUXIN3" 181 PIN 91: "TXD4" 182 PIN 92: "RXD4" 183 PIN 93: "RTS4_N" 184 PIN 94: "CST4_N" 185 PIN 95: "PWM1" 186 PIN 96: "PWM2" 187 PIN 97: "PWM3" 188 PIN 98: "PWM4" 189 PIN 99: "PWM5" 190 PIN 100: "PWM6" 191 PIN 101: "PWM7" 192 PIN 102: "GPIO_E" 193 194Valid values for function are: 195 "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie", 196 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog" 197 198Valid values for groups are: 199additional data is put followingly with valid value allowing us to know which 200applicable function and which relevant pins (in pin#) are able applied for that 201group. 202 203 Valid value function pins (in pin#) 204 ------------------------------------------------------------------------- 205 "emmc" "emmc" 40, 41, 42, 43, 44, 45, 206 47, 48, 49, 50 207 "emmc_rst" "emmc" 37 208 "esw" "eth" 51, 52, 53, 54, 55, 56, 209 57, 58, 59, 60, 61, 62, 210 63, 64, 65, 66, 67, 68, 211 69, 70 212 "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56, 213 57, 58 214 "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64, 215 65, 66, 67, 68, 69, 70 216 "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64, 217 65, 66, 67, 68, 69, 70 218 "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64, 219 65, 66, 67, 68, 69, 70 220 "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30, 221 31, 32, 33, 34, 35, 36 222 "mdc_mdio" "eth" 23, 24 223 "i2c0" "i2c" 14, 15 224 "i2c1_0" "i2c" 55, 56 225 "i2c1_1" "i2c" 73, 74 226 "i2c1_2" "i2c" 87, 88 227 "i2c2_0" "i2c" 57, 58 228 "i2c2_1" "i2c" 75, 76 229 "i2c2_2" "i2c" 89, 90 230 "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5 231 "i2s1_in_data" "i2s" 1 232 "i2s2_in_data" "i2s" 16 233 "i2s3_in_data" "i2s" 17 234 "i2s4_in_data" "i2s" 18 235 "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5 236 "i2s1_out_data" "i2s" 2 237 "i2s2_out_data" "i2s" 19 238 "i2s3_out_data" "i2s" 20 239 "i2s4_out_data" "i2s" 21 240 "ir_0_tx" "ir" 16 241 "ir_1_tx" "ir" 59 242 "ir_2_tx" "ir" 99 243 "ir_0_rx" "ir" 17 244 "ir_1_rx" "ir" 60 245 "ir_2_rx" "ir" 100 246 "ephy_leds" "led" 86, 91, 92, 93, 94 247 "ephy0_led" "led" 86 248 "ephy1_led" "led" 91 249 "ephy2_led" "led" 92 250 "ephy3_led" "led" 93 251 "ephy4_led" "led" 94 252 "wled" "led" 85 253 "par_nand" "flash" 37, 38, 39, 40, 41, 42, 254 43, 44, 45, 46, 47, 48, 255 49, 50 256 "snfi" "flash" 8, 9, 10, 11, 12, 13 257 "spi_nor" "flash" 8, 9, 10, 11, 12, 13 258 "pcie0_0_waken" "pcie" 14 259 "pcie0_1_waken" "pcie" 79 260 "pcie1_0_waken" "pcie" 14 261 "pcie0_0_clkreq" "pcie" 15 262 "pcie0_1_clkreq" "pcie" 80 263 "pcie1_0_clkreq" "pcie" 15 264 "pcie0_pad_perst" "pcie" 83 265 "pcie1_pad_perst" "pcie" 84 266 "pmic_bus" "pmic" 71, 72 267 "pwm_ch1_0" "pwm" 51 268 "pwm_ch1_1" "pwm" 73 269 "pwm_ch1_2" "pwm" 95 270 "pwm_ch2_0" "pwm" 52 271 "pwm_ch2_1" "pwm" 74 272 "pwm_ch2_2" "pwm" 96 273 "pwm_ch3_0" "pwm" 53 274 "pwm_ch3_1" "pwm" 75 275 "pwm_ch3_2" "pwm" 97 276 "pwm_ch4_0" "pwm" 54 277 "pwm_ch4_1" "pwm" 67 278 "pwm_ch4_2" "pwm" 76 279 "pwm_ch4_3" "pwm" 98 280 "pwm_ch5_0" "pwm" 68 281 "pwm_ch5_1" "pwm" 77 282 "pwm_ch5_2" "pwm" 99 283 "pwm_ch6_0" "pwm" 69 284 "pwm_ch6_1" "pwm" 78 285 "pwm_ch6_2" "pwm" 81 286 "pwm_ch6_3" "pwm" 100 287 "pwm_ch7_0" "pwm" 70 288 "pwm_ch7_1" "pwm" 82 289 "pwm_ch7_2" "pwm" 101 290 "sd_0" "sd" 16, 17, 18, 19, 20, 21 291 "sd_1" "sd" 25, 26, 27, 28, 29, 30 292 "spic0_0" "spi" 63, 64, 65, 66 293 "spic0_1" "spi" 79, 80, 81, 82 294 "spic1_0" "spi" 67, 68, 69, 70 295 "spic1_1" "spi" 73, 74, 75, 76 296 "spic2_0_wp_hold" "spi" 8, 9 297 "spic2_0" "spi" 10, 11, 12, 13 298 "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10 299 "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13 300 "tdm_0_out_data" "tdm" 20 301 "tdm_0_in_data" "tdm" 21 302 "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59 303 "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62 304 "tdm_1_out_data" "tdm" 55 305 "tdm_1_in_data" "tdm" 56 306 "uart0_0_tx_rx" "uart" 6, 7 307 "uart1_0_tx_rx" "uart" 55, 56 308 "uart1_0_rts_cts" "uart" 57, 58 309 "uart1_1_tx_rx" "uart" 73, 74 310 "uart1_1_rts_cts" "uart" 75, 76 311 "uart2_0_tx_rx" "uart" 3, 4 312 "uart2_0_rts_cts" "uart" 1, 2 313 "uart2_1_tx_rx" "uart" 51, 52 314 "uart2_1_rts_cts" "uart" 53, 54 315 "uart2_2_tx_rx" "uart" 59, 60 316 "uart2_2_rts_cts" "uart" 61, 62 317 "uart2_3_tx_rx" "uart" 95, 96 318 "uart3_0_tx_rx" "uart" 57, 58 319 "uart3_1_tx_rx" "uart" 81, 82 320 "uart3_1_rts_cts" "uart" 79, 80 321 "uart4_0_tx_rx" "uart" 61, 62 322 "uart4_1_tx_rx" "uart" 91, 92 323 "uart4_1_rts_cts" "uart" 93, 94 324 "uart4_2_tx_rx" "uart" 97, 98 325 "uart4_2_rts_cts" "uart" 95, 96 326 "watchdog" "watchdog" 78 327 328 329== Valid values for pins, function and groups on MT7629 == 330 331 Pin #: Valid values for pins 332 ----------------------------- 333 PIN 0: "TOP_5G_CLK" 334 PIN 1: "TOP_5G_DATA" 335 PIN 2: "WF0_5G_HB0" 336 PIN 3: "WF0_5G_HB1" 337 PIN 4: "WF0_5G_HB2" 338 PIN 5: "WF0_5G_HB3" 339 PIN 6: "WF0_5G_HB4" 340 PIN 7: "WF0_5G_HB5" 341 PIN 8: "WF0_5G_HB6" 342 PIN 9: "XO_REQ" 343 PIN 10: "TOP_RST_N" 344 PIN 11: "SYS_WATCHDOG" 345 PIN 12: "EPHY_LED0_N_JTDO" 346 PIN 13: "EPHY_LED1_N_JTDI" 347 PIN 14: "EPHY_LED2_N_JTMS" 348 PIN 15: "EPHY_LED3_N_JTCLK" 349 PIN 16: "EPHY_LED4_N_JTRST_N" 350 PIN 17: "WF2G_LED_N" 351 PIN 18: "WF5G_LED_N" 352 PIN 19: "I2C_SDA" 353 PIN 20: "I2C_SCL" 354 PIN 21: "GPIO_9" 355 PIN 22: "GPIO_10" 356 PIN 23: "GPIO_11" 357 PIN 24: "GPIO_12" 358 PIN 25: "UART1_TXD" 359 PIN 26: "UART1_RXD" 360 PIN 27: "UART1_CTS" 361 PIN 28: "UART1_RTS" 362 PIN 29: "UART2_TXD" 363 PIN 30: "UART2_RXD" 364 PIN 31: "UART2_CTS" 365 PIN 32: "UART2_RTS" 366 PIN 33: "MDI_TP_P1" 367 PIN 34: "MDI_TN_P1" 368 PIN 35: "MDI_RP_P1" 369 PIN 36: "MDI_RN_P1" 370 PIN 37: "MDI_RP_P2" 371 PIN 38: "MDI_RN_P2" 372 PIN 39: "MDI_TP_P2" 373 PIN 40: "MDI_TN_P2" 374 PIN 41: "MDI_TP_P3" 375 PIN 42: "MDI_TN_P3" 376 PIN 43: "MDI_RP_P3" 377 PIN 44: "MDI_RN_P3" 378 PIN 45: "MDI_RP_P4" 379 PIN 46: "MDI_RN_P4" 380 PIN 47: "MDI_TP_P4" 381 PIN 48: "MDI_TN_P4" 382 PIN 49: "SMI_MDC" 383 PIN 50: "SMI_MDIO" 384 PIN 51: "PCIE_PERESET_N" 385 PIN 52: "PWM_0" 386 PIN 53: "GPIO_0" 387 PIN 54: "GPIO_1" 388 PIN 55: "GPIO_2" 389 PIN 56: "GPIO_3" 390 PIN 57: "GPIO_4" 391 PIN 58: "GPIO_5" 392 PIN 59: "GPIO_6" 393 PIN 60: "GPIO_7" 394 PIN 61: "GPIO_8" 395 PIN 62: "SPI_CLK" 396 PIN 63: "SPI_CS" 397 PIN 64: "SPI_MOSI" 398 PIN 65: "SPI_MISO" 399 PIN 66: "SPI_WP" 400 PIN 67: "SPI_HOLD" 401 PIN 68: "UART0_TXD" 402 PIN 69: "UART0_RXD" 403 PIN 70: "TOP_2G_CLK" 404 PIN 71: "TOP_2G_DATA" 405 PIN 72: "WF0_2G_HB0" 406 PIN 73: "WF0_2G_HB1" 407 PIN 74: "WF0_2G_HB2" 408 PIN 75: "WF0_2G_HB3" 409 PIN 76: "WF0_2G_HB4" 410 PIN 77: "WF0_2G_HB5" 411 PIN 78: "WF0_2G_HB6" 412 413Valid values for function are: 414 "eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart", 415 "watchdog", "wifi" 416 417Valid values for groups are: 418 Valid value function pins (in pin#) 419 ---------------------------------------------------------------- 420 "mdc_mdio" "eth" 23, 24 421 "i2c_0" "i2c" 19, 20 422 "i2c_1" "i2c" 53, 54 423 "ephy_leds" "led" 12, 13, 14, 15, 16, 424 17, 18 425 "ephy0_led" "led" 12 426 "ephy1_led" "led" 13 427 "ephy2_led" "led" 14 428 "ephy3_led" "led" 15 429 "ephy4_led" "led" 16 430 "wf2g_led" "led" 17 431 "wf5g_led" "led" 18 432 "snfi" "flash" 62, 63, 64, 65, 66, 67 433 "spi_nor" "flash" 62, 63, 64, 65, 66, 67 434 "pcie_pereset" "pcie" 51 435 "pcie_wake" "pcie" 55 436 "pcie_clkreq" "pcie" 56 437 "pwm_0" "pwm" 52 438 "pwm_1" "pwm" 61 439 "spi_0" "spi" 21, 22, 23, 24 440 "spi_1" "spi" 62, 63, 64, 65 441 "spi_wp" "spi" 66 442 "spi_hold" "spi" 67 443 "uart0_txd_rxd" "uart" 68, 69 444 "uart1_0_txd_rxd" "uart" 25, 26 445 "uart1_0_cts_rts" "uart" 27, 28 446 "uart1_1_txd_rxd" "uart" 53, 54 447 "uart1_1_cts_rts" "uart" 55, 56 448 "uart2_0_txd_rxd" "uart" 29, 30 449 "uart2_0_cts_rts" "uart" 31, 32 450 "uart2_1_txd_rxd" "uart" 57, 58 451 "uart2_1_cts_rts" "uart" 59, 60 452 "watchdog" "watchdog" 11 453 "wf0_2g" "wifi" 70, 71, 72, 73, 74, 454 75, 76, 77, 78 455 "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, 456 7, 8, 9, 10 457 458Example: 459 460 pio: pinctrl@10211000 { 461 compatible = "mediatek,mt7622-pinctrl"; 462 reg = <0 0x10211000 0 0x1000>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 466 pinctrl_eth_default: eth-default { 467 mux-mdio { 468 groups = "mdc_mdio"; 469 function = "eth"; 470 drive-strength = <12>; 471 }; 472 473 mux-gmac2 { 474 groups = "gmac2"; 475 function = "eth"; 476 drive-strength = <12>; 477 }; 478 479 mux-esw { 480 groups = "esw"; 481 function = "eth"; 482 drive-strength = <8>; 483 }; 484 485 conf-mdio { 486 pins = "MDC"; 487 bias-pull-up; 488 }; 489 }; 490 }; 491