1* Mediatek MT65XX Pin Controller 2 3The Mediatek's Pin controller is used to control SoC pins. 4 5Required properties: 6- compatible: value should be one of the following. 7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. 8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. 9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. 10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. 11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. 12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. 13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. 14 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. 15- pins-are-numbered: Specify the subnodes are using numbered pinmux to 16 specify pins. 17- gpio-controller : Marks the device node as a gpio controller. 18- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 19 binding is used, the amount of cells must be specified as 2. See the below 20 mentioned gpio binding representation for description of particular cells. 21 22 Eg: <&pio 6 0> 23 <[phandle of the gpio controller node] 24 [line number within the gpio controller] 25 [flags]> 26 27 Values for gpio specifier: 28 - Line number: is a value between 0 to 202. 29 - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>. 30 Only the following flags are supported: 31 0 - GPIO_ACTIVE_HIGH 32 1 - GPIO_ACTIVE_LOW 33 34Optional properties: 35- mediatek,pctl-regmap: Should be a phandle of the syscfg node. 36- reg: physicall address base for EINT registers 37- interrupt-controller: Marks the device node as an interrupt controller 38- #interrupt-cells: Should be two. 39- interrupts : The interrupt outputs from the controller. 40 41Please refer to pinctrl-bindings.txt in this directory for details of the 42common pinctrl bindings used by client devices. 43 44Subnode format 45A pinctrl node should contain at least one subnodes representing the 46pinctrl groups available on the machine. Each subnode will list the 47pins it needs, and how they should be configured, with regard to muxer 48configuration, pullups, drive strength, input enable/disable and input schmitt. 49 50 node { 51 pinmux = <PIN_NUMBER_PINMUX>; 52 GENERIC_PINCONFIG; 53 }; 54 55Required properties: 56- pinmux: integer array, represents gpio pin number and mux setting. 57 Supported pin number and mux varies for different SoCs, and are defined 58 as macros in boot/dts/<soc>-pinfunc.h directly. 59 60Optional properties: 61- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, 62 bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, 63 input-schmitt-enable, input-schmitt-disable and drive-strength are valid. 64 65 Some special pins have extra pull up strength, there are R0 and R1 pull-up 66 resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. 67 So when config bias-pull-up, it support arguments for those special pins. 68 Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00. 69 See dt-bindings/pinctrl/mt65xx.h. 70 71 When config drive-strength, it can support some arguments, such as 72 MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. 73 74Examples: 75 76#include "mt8135-pinfunc.h" 77 78... 79{ 80 syscfg_pctl_a: syscfg-pctl-a@10005000 { 81 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; 82 reg = <0 0x10005000 0 0x1000>; 83 }; 84 85 syscfg_pctl_b: syscfg-pctl-b@1020c020 { 86 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; 87 reg = <0 0x1020C020 0 0x1000>; 88 }; 89 90 pinctrl@1c20800 { 91 compatible = "mediatek,mt8135-pinctrl"; 92 reg = <0 0x1000B000 0 0x1000>; 93 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; 94 pins-are-numbered; 95 gpio-controller; 96 #gpio-cells = <2>; 97 interrupt-controller; 98 #interrupt-cells = <2>; 99 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 102 103 i2c0_pins_a: i2c0@0 { 104 pins1 { 105 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, 106 <MT8135_PIN_101_SCL0__FUNC_SCL0>; 107 bias-disable; 108 }; 109 }; 110 111 i2c1_pins_a: i2c1@0 { 112 pins { 113 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, 114 <MT8135_PIN_196_SCL1__FUNC_SCL1>; 115 bias-pull-up = <55>; 116 }; 117 }; 118 119 i2c2_pins_a: i2c2@0 { 120 pins1 { 121 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; 122 bias-pull-down; 123 }; 124 125 pins2 { 126 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; 127 bias-pull-up; 128 }; 129 }; 130 131 i2c3_pins_a: i2c3@0 { 132 pins1 { 133 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, 134 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; 135 bias-pull-up = <55>; 136 }; 137 138 pins2 { 139 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, 140 <MT8135_PIN_36_SDA3__FUNC_SDA3>; 141 output-low; 142 bias-pull-up = <55>; 143 }; 144 145 pins3 { 146 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, 147 <MT8135_PIN_60_JTDI__FUNC_JTDI>; 148 drive-strength = <32>; 149 }; 150 }; 151 152 ... 153 } 154}; 155