1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: The Tegra124 pinctrl binding is very similar to the Tegra20 and 14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and 15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a 16 baseline, and only documents the differences between the two bindings. 17 18properties: 19 compatible: 20 oneOf: 21 - const: nvidia,tegra124-pinmux 22 - items: 23 - const: nvidia,tegra132-pinmux 24 - const: nvidia,tegra124-pinmux 25 26 reg: 27 items: 28 - description: driver strength and pad control registers 29 - description: pinmux registers 30 - description: MIPI_PAD_CTRL registers 31 32patternProperties: 33 "^pinmux(-[a-z0-9-_]+)?$": 34 type: object 35 36 # pin groups 37 additionalProperties: 38 $ref: nvidia,tegra-pinmux-common.yaml 39 additionalProperties: false 40 properties: 41 nvidia,pins: 42 $ref: /schemas/types.yaml#/definitions/string-array 43 items: 44 enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, 45 ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, 46 ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1, 47 ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1, 48 dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, 49 sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, 50 sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5, 51 clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5, 52 uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, 53 uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, 54 uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, 55 pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4, 56 dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0, 57 clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4, 58 pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0, 59 ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, 60 pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, 61 sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, 62 sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, 63 sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, 64 sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, 65 cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, 66 pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, 67 kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, 68 kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, 69 kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, 70 kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, 71 kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, 72 kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7, 73 clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, 74 clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, 75 dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, 76 spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, 77 dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, 78 gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, 79 gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, 80 gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, 81 sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, 82 sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, 83 pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6, 84 hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2, 85 gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, 86 usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, 87 sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n, 88 kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2, 89 dp_hpd_pff0, 90 # drive groups 91 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, 92 drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1, 93 drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3, 94 drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, 95 drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf, 96 drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv, 97 drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3, 98 drive_ao0, drive_hv0, drive_sdio4, drive_ao4, 99 # MIPI pad control groups 100 mipi_pad_ctrl_dsi_b ] 101 102 nvidia,function: 103 enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, 104 displaya, displaya_alt, displayb, dtv, extperiph1, 105 extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, 106 i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, 107 owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, 108 rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, 109 spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, 110 uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, 111 vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, 112 pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ] 113 114 nvidia,pull: true 115 nvidia,tristate: true 116 nvidia,schmitt: true 117 nvidia,pull-down-strength: true 118 nvidia,pull-up-strength: true 119 nvidia,high-speed-mode: true 120 nvidia,low-power-mode: true 121 nvidia,enable-input: true 122 nvidia,open-drain: true 123 nvidia,lock: true 124 nvidia,io-reset: true 125 nvidia,rcv-sel: true 126 nvidia,drive-type: true 127 nvidia,slew-rate-rising: true 128 nvidia,slew-rate-falling: true 129 130 required: 131 - nvidia,pins 132 133additionalProperties: false 134 135required: 136 - compatible 137 - reg 138 139examples: 140 - | 141 #include <dt-bindings/clock/tegra124-car.h> 142 #include <dt-bindings/interrupt-controller/arm-gic.h> 143 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 144 145 pinmux@70000868 { 146 compatible = "nvidia,tegra124-pinmux"; 147 reg = <0x70000868 0x164>, /* Pad control registers */ 148 <0x70003000 0x434>, /* Mux registers */ 149 <0x70000820 0x8>; /* MIPI pad control */ 150 151 sdmmc4_default: pinmux { 152 sdmmc4_clk_pcc4 { 153 nvidia,pins = "sdmmc4_clk_pcc4"; 154 nvidia,function = "sdmmc4"; 155 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156 nvidia,tristate = <TEGRA_PIN_DISABLE>; 157 }; 158 159 sdmmc4_dat0_paa0 { 160 nvidia,pins = "sdmmc4_dat0_paa0", 161 "sdmmc4_dat1_paa1", 162 "sdmmc4_dat2_paa2", 163 "sdmmc4_dat3_paa3", 164 "sdmmc4_dat4_paa4", 165 "sdmmc4_dat5_paa5", 166 "sdmmc4_dat6_paa6", 167 "sdmmc4_dat7_paa7"; 168 nvidia,function = "sdmmc4"; 169 nvidia,pull = <TEGRA_PIN_PULL_UP>; 170 nvidia,tristate = <TEGRA_PIN_DISABLE>; 171 }; 172 }; 173 }; 174... 175