1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra114 pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 const: nvidia,tegra114-pinmux 16 17 reg: 18 items: 19 - description: pad control registers 20 - description: mux registers 21 22patternProperties: 23 "^pinmux(-[a-z0-9-_]+)?$": 24 type: object 25 properties: 26 phandle: true 27 28 # pin groups 29 additionalProperties: 30 $ref: nvidia,tegra-pinmux-common.yaml 31 additionalProperties: false 32 properties: 33 nvidia,pins: 34 items: 35 enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, 36 ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, 37 ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1, 38 ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1, 39 dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, 40 sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, 41 sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5, 42 clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5, 43 uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, 44 uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, 45 uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, 46 pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4, 47 dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0, 48 clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7, 49 gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, 50 gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, 51 gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2, 52 gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6, 53 gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, 54 gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, 55 gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, 56 gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3, 57 gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, 58 sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, 59 sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, 60 sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, 61 sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, 62 cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, 63 pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, 64 kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, 65 kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, 66 kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1, 67 kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, 68 kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, 69 core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, 70 dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2, 71 clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, 72 dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, 73 gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, 74 gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, 75 gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, 76 sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, 77 sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, 78 sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, 79 usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5, 80 sdmmc3_clk_lb_out_pee4, reset_out_n, 81 # drive groups 82 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, 83 drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1, 84 drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3, 85 drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, 86 drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf, 87 drive_gmg, drive_gmh, drive_owr, drive_uda ] 88 89 nvidia,function: 90 enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, 91 displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1, 92 extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, 93 i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, 94 nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, 95 reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, 96 sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, 97 spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb, 98 vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ] 99 100 nvidia,pull: true 101 nvidia,tristate: true 102 nvidia,schmitt: true 103 nvidia,pull-down-strength: true 104 nvidia,pull-up-strength: true 105 nvidia,high-speed-mode: true 106 nvidia,low-power-mode: true 107 nvidia,enable-input: true 108 nvidia,open-drain: true 109 nvidia,lock: true 110 nvidia,io-reset: true 111 nvidia,rcv-sel: true 112 nvidia,drive-type: true 113 nvidia,slew-rate-rising: true 114 nvidia,slew-rate-falling: true 115 116 required: 117 - nvidia,pins 118 119additionalProperties: false 120 121required: 122 - compatible 123 - reg 124 125examples: 126 - | 127 pinmux@70000868 { 128 compatible = "nvidia,tegra114-pinmux"; 129 reg = <0x70000868 0x148>, /* Pad control registers */ 130 <0x70003000 0x40c>; /* PinMux registers */ 131 132 pinmux { 133 sdmmc4_clk_pcc4 { 134 nvidia,pins = "sdmmc4_clk_pcc4"; 135 nvidia,function = "sdmmc4"; 136 nvidia,pull = <0>; 137 nvidia,tristate = <0>; 138 }; 139 140 sdmmc4_dat0_paa0 { 141 nvidia,pins = "sdmmc4_dat0_paa0", 142 "sdmmc4_dat1_paa1", 143 "sdmmc4_dat2_paa2", 144 "sdmmc4_dat3_paa3", 145 "sdmmc4_dat4_paa4", 146 "sdmmc4_dat5_paa5", 147 "sdmmc4_dat6_paa6", 148 "sdmmc4_dat7_paa7"; 149 nvidia,function = "sdmmc4"; 150 nvidia,pull = <2>; 151 nvidia,tristate = <0>; 152 }; 153 }; 154 }; 155... 156