xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/microchip,sparx5-sgpio.yaml (revision acb1f1269c6f4ff89a0d28ba742f6687e9ef779d) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microsemi/Microchip Serial GPIO controller
8
9maintainers:
10  - Lars Povlsen <lars.povlsen@microchip.com>
11
12description: |
13  By using a serial interface, the SIO controller significantly extend
14  the number of available GPIOs with a minimum number of additional
15  pins on the device. The primary purpose of the SIO controllers is to
16  connect control signals from SFP modules and to act as an LED
17  controller.
18
19properties:
20  $nodename:
21    pattern: "^gpio@[0-9a-f]+$"
22
23  compatible:
24    enum:
25      - microchip,sparx5-sgpio
26      - mscc,ocelot-sgpio
27      - mscc,luton-sgpio
28
29  "#address-cells":
30    const: 1
31
32  "#size-cells":
33    const: 0
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    maxItems: 1
40
41  microchip,sgpio-port-ranges:
42    description: This is a sequence of tuples, defining intervals of
43      enabled ports in the serial input stream. The enabled ports must
44      match the hardware configuration in order for signals to be
45      properly written/read to/from the controller holding
46      registers. Being tuples, then number of arguments must be
47      even. The tuples mast be ordered (low, high) and are
48      inclusive.
49    $ref: /schemas/types.yaml#/definitions/uint32-matrix
50    items:
51      items:
52        - description: |
53            "low" indicates start bit number of range
54          minimum: 0
55          maximum: 31
56        - description: |
57            "high" indicates end bit number of range
58          minimum: 0
59          maximum: 31
60    minItems: 1
61    maxItems: 32
62
63  bus-frequency:
64    description: The sgpio controller frequency (Hz). This dictates
65      the serial bitstream speed, which again affects the latency in
66      getting control signals back and forth between external shift
67      registers. The speed must be no larger than half the system
68      clock, and larger than zero.
69    default: 12500000
70
71patternProperties:
72  "^gpio@[0-1]$":
73    type: object
74    properties:
75      compatible:
76        const: microchip,sparx5-sgpio-bank
77
78      reg:
79        description: |
80          The GPIO bank number. "0" is designates the input pin bank,
81          "1" the output bank.
82        maxItems: 1
83
84      gpio-controller: true
85
86      '#gpio-cells':
87        description: |
88         Specifies the pin (port and bit) and flags. Note that the
89         SGIO pin is defined by *2* numbers, a port number between 0
90         and 31, and a bit index, 0 to 3. The maximum bit number is
91         controlled indirectly by the "ngpios" property: (ngpios/32).
92        const: 3
93
94      interrupts:
95        description: Specifies the sgpio IRQ (in parent controller)
96        maxItems: 1
97
98      interrupt-controller: true
99
100      '#interrupt-cells':
101        description:
102          Specifies the pin (port and bit) and flags, as defined in
103          defined in include/dt-bindings/interrupt-controller/irq.h
104        const: 3
105
106      ngpios:
107        description: The numbers of GPIO's exposed. This must be a
108          multiple of 32.
109        minimum: 32
110        maximum: 128
111
112    required:
113      - compatible
114      - reg
115      - gpio-controller
116      - '#gpio-cells'
117      - ngpios
118
119    additionalProperties: false
120
121additionalProperties: false
122
123required:
124  - compatible
125  - reg
126  - clocks
127  - microchip,sgpio-port-ranges
128  - "#address-cells"
129  - "#size-cells"
130
131examples:
132  - |
133    #include <dt-bindings/interrupt-controller/arm-gic.h>
134    sgpio2: gpio@1101059c {
135      #address-cells = <1>;
136      #size-cells = <0>;
137      compatible = "microchip,sparx5-sgpio";
138      clocks = <&sys_clk>;
139      pinctrl-0 = <&sgpio2_pins>;
140      pinctrl-names = "default";
141      reg = <0x1101059c 0x100>;
142      microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
143      bus-frequency = <25000000>;
144      sgpio_in2: gpio@0 {
145        reg = <0>;
146        compatible = "microchip,sparx5-sgpio-bank";
147        gpio-controller;
148        #gpio-cells = <3>;
149        ngpios = <96>;
150        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
151        interrupt-controller;
152        #interrupt-cells = <3>;
153      };
154      sgpio_out2: gpio@1 {
155        compatible = "microchip,sparx5-sgpio-bank";
156        reg = <1>;
157        gpio-controller;
158        #gpio-cells = <3>;
159        ngpios = <96>;
160      };
161    };
162