1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek MT6795 Pin Controller 8 9maintainers: 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 11 - Sean Wang <sean.wang@kernel.org> 12 13description: 14 The MediaTek's MT6795 Pin controller is used to control SoC pins. 15 16properties: 17 compatible: 18 const: mediatek,mt6795-pinctrl 19 20 gpio-controller: true 21 22 '#gpio-cells': 23 description: 24 Number of cells in GPIO specifier. Since the generic GPIO binding is used, 25 the amount of cells must be specified as 2. See the below mentioned gpio 26 binding representation for description of particular cells. 27 const: 2 28 29 gpio-ranges: 30 description: GPIO valid number range. 31 maxItems: 1 32 33 reg: 34 description: 35 Physical address base for GPIO base and eint registers. 36 minItems: 2 37 38 reg-names: 39 items: 40 - const: base 41 - const: eint 42 43 interrupt-controller: true 44 45 '#interrupt-cells': 46 const: 2 47 48 interrupts: 49 description: Interrupt outputs to the system interrupt controller (sysirq). 50 minItems: 1 51 items: 52 - description: EINT interrupt 53 - description: EINT event_b interrupt 54 55# PIN CONFIGURATION NODES 56patternProperties: 57 '-pins$': 58 type: object 59 additionalProperties: false 60 patternProperties: 61 '^pins': 62 type: object 63 additionalProperties: false 64 description: | 65 A pinctrl node should contain at least one subnodes representing the 66 pinctrl groups available on the machine. Each subnode will list the 67 pins it needs, and how they should be configured, with regard to muxer 68 configuration, pullups, drive strength, input enable/disable and input 69 schmitt. 70 An example of using macro: 71 pincontroller { 72 /* GPIO0 set as multifunction GPIO0 */ 73 gpio-pins { 74 pins { 75 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; 76 } 77 }; 78 /* GPIO45 set as multifunction SDA0 */ 79 i2c0-pins { 80 pins { 81 pinmux = <PINMUX_GPIO45__FUNC_SDA0>; 82 } 83 }; 84 }; 85 $ref: pinmux-node.yaml 86 87 properties: 88 pinmux: 89 description: 90 Integer array, represents gpio pin number and mux setting. 91 Supported pin number and mux varies for different SoCs, and are 92 defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 93 94 drive-strength: 95 enum: [2, 4, 6, 8, 10, 12, 14, 16] 96 97 bias-pull-down: 98 oneOf: 99 - type: boolean 100 - enum: [100, 101, 102, 103] 101 description: mt6795 pull down PUPD/R0/R1 type define value. 102 description: 103 For normal pull down type, it is not necessary to specify R1R0 104 values; When pull down type is PUPD/R0/R1, adding R1R0 defines 105 will set different resistance values. 106 107 bias-pull-up: 108 oneOf: 109 - type: boolean 110 - enum: [100, 101, 102, 103] 111 description: mt6795 pull up PUPD/R0/R1 type define value. 112 description: 113 For normal pull up type, it is not necessary to specify R1R0 114 values; When pull up type is PUPD/R0/R1, adding R1R0 defines will 115 set different resistance values. 116 117 bias-disable: true 118 119 output-high: true 120 121 output-low: true 122 123 input-enable: true 124 125 input-disable: true 126 127 input-schmitt-enable: true 128 129 input-schmitt-disable: true 130 131 mediatek,pull-up-adv: 132 description: | 133 Pull up settings for 2 pull resistors, R0 and R1. User can 134 configure those special pins. Valid arguments are described as 135 below: 136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 139 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 140 $ref: /schemas/types.yaml#/definitions/uint32 141 enum: [0, 1, 2, 3] 142 143 mediatek,pull-down-adv: 144 description: | 145 Pull down settings for 2 pull resistors, R0 and R1. User can 146 configure those special pins. Valid arguments are described as 147 below: 148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 149 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 150 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 151 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 152 $ref: /schemas/types.yaml#/definitions/uint32 153 enum: [0, 1, 2, 3] 154 155 required: 156 - pinmux 157 158allOf: 159 - $ref: pinctrl.yaml# 160 161required: 162 - compatible 163 - reg 164 - reg-names 165 - interrupts 166 - interrupt-controller 167 - '#interrupt-cells' 168 - gpio-controller 169 - '#gpio-cells' 170 - gpio-ranges 171 172additionalProperties: false 173 174examples: 175 - | 176 #include <dt-bindings/interrupt-controller/arm-gic.h> 177 #include <dt-bindings/interrupt-controller/irq.h> 178 #include <dt-bindings/pinctrl/mt6795-pinfunc.h> 179 180 soc { 181 #address-cells = <2>; 182 #size-cells = <2>; 183 184 pio: pinctrl@10005000 { 185 compatible = "mediatek,mt6795-pinctrl"; 186 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 187 reg-names = "base", "eint"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 gpio-ranges = <&pio 0 0 196>; 191 interrupt-controller; 192 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 193 #interrupt-cells = <2>; 194 195 i2c0-pins { 196 pins-sda-scl { 197 pinmux = <PINMUX_GPIO45__FUNC_SDA0>, 198 <PINMUX_GPIO46__FUNC_SCL0>; 199 }; 200 }; 201 202 mmc0-pins { 203 pins-cmd-dat { 204 pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>, 205 <PINMUX_GPIO155__FUNC_MSDC0_DAT1>, 206 <PINMUX_GPIO156__FUNC_MSDC0_DAT2>, 207 <PINMUX_GPIO157__FUNC_MSDC0_DAT3>, 208 <PINMUX_GPIO158__FUNC_MSDC0_DAT4>, 209 <PINMUX_GPIO159__FUNC_MSDC0_DAT5>, 210 <PINMUX_GPIO160__FUNC_MSDC0_DAT6>, 211 <PINMUX_GPIO161__FUNC_MSDC0_DAT7>, 212 <PINMUX_GPIO162__FUNC_MSDC0_CMD>; 213 input-enable; 214 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 215 }; 216 217 pins-clk { 218 pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>; 219 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 220 }; 221 222 pins-rst { 223 pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>; 224 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 225 }; 226 }; 227 }; 228 }; 229