1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT6779 Pin Controller Device Tree Bindings 8 9maintainers: 10 - Andy Teng <andy.teng@mediatek.com> 11 12description: |+ 13 The pin controller node should be the child of a syscon node with the 14 required property: 15 - compatible: "syscon" 16 17properties: 18 compatible: 19 const: mediatek,mt6779-pinctrl 20 21 reg: 22 minItems: 9 23 maxItems: 9 24 25 reg-names: 26 items: 27 - const: "gpio" 28 - const: "iocfg_rm" 29 - const: "iocfg_br" 30 - const: "iocfg_lm" 31 - const: "iocfg_lb" 32 - const: "iocfg_rt" 33 - const: "iocfg_lt" 34 - const: "iocfg_tl" 35 - const: "eint" 36 37 gpio-controller: true 38 39 "#gpio-cells": 40 const: 2 41 description: | 42 Number of cells in GPIO specifier. Since the generic GPIO 43 binding is used, the amount of cells must be specified as 2. See the below 44 mentioned gpio binding representation for description of particular cells. 45 46 gpio-ranges: 47 minItems: 1 48 maxItems: 5 49 description: | 50 GPIO valid number range. 51 52 interrupt-controller: true 53 54 interrupts: 55 maxItems: 1 56 description: | 57 Specifies the summary IRQ. 58 59 "#interrupt-cells": 60 const: 2 61 62required: 63 - compatible 64 - reg 65 - reg-names 66 - gpio-controller 67 - "#gpio-cells" 68 - gpio-ranges 69 - interrupt-controller 70 - interrupts 71 - "#interrupt-cells" 72 73patternProperties: 74 '-[0-9]*$': 75 type: object 76 patternProperties: 77 '-pins*$': 78 type: object 79 description: | 80 A pinctrl node should contain at least one subnodes representing the 81 pinctrl groups available on the machine. Each subnode will list the 82 pins it needs, and how they should be configured, with regard to muxer 83 configuration, pullups, drive strength, input enable/disable and input schmitt. 84 $ref: "/schemas/pinctrl/pincfg-node.yaml" 85 86 properties: 87 pinmux: 88 description: 89 integer array, represents gpio pin number and mux setting. 90 Supported pin number and mux varies for different SoCs, and are defined 91 as macros in boot/dts/<soc>-pinfunc.h directly. 92 93 bias-disable: true 94 95 bias-pull-up: true 96 97 bias-pull-down: true 98 99 input-enable: true 100 101 input-disable: true 102 103 output-low: true 104 105 output-high: true 106 107 input-schmitt-enable: true 108 109 input-schmitt-disable: true 110 111 mediatek,pull-up-adv: 112 description: | 113 Pull up setings for 2 pull resistors, R0 and R1. User can 114 configure those special pins. Valid arguments are described as below: 115 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 116 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 117 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 118 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 119 $ref: /schemas/types.yaml#/definitions/uint32 120 enum: [0, 1, 2, 3] 121 122 mediatek,pull-down-adv: 123 description: | 124 Pull down settings for 2 pull resistors, R0 and R1. User can 125 configure those special pins. Valid arguments are described as below: 126 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 127 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 128 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 129 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 130 $ref: /schemas/types.yaml#/definitions/uint32 131 enum: [0, 1, 2, 3] 132 133 required: 134 - pinmux 135 136 additionalProperties: false 137 138additionalProperties: false 139 140examples: 141 - | 142 #include <dt-bindings/interrupt-controller/irq.h> 143 #include <dt-bindings/interrupt-controller/arm-gic.h> 144 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 145 146 soc { 147 #address-cells = <2>; 148 #size-cells = <2>; 149 150 pio: pinctrl@10005000 { 151 compatible = "mediatek,mt6779-pinctrl"; 152 reg = <0 0x10005000 0 0x1000>, 153 <0 0x11c20000 0 0x1000>, 154 <0 0x11d10000 0 0x1000>, 155 <0 0x11e20000 0 0x1000>, 156 <0 0x11e70000 0 0x1000>, 157 <0 0x11ea0000 0 0x1000>, 158 <0 0x11f20000 0 0x1000>, 159 <0 0x11f30000 0 0x1000>, 160 <0 0x1000b000 0 0x1000>; 161 reg-names = "gpio", "iocfg_rm", 162 "iocfg_br", "iocfg_lm", 163 "iocfg_lb", "iocfg_rt", 164 "iocfg_lt", "iocfg_tl", 165 "eint"; 166 gpio-controller; 167 #gpio-cells = <2>; 168 gpio-ranges = <&pio 0 0 210>; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 172 173 mmc0_pins_default: mmc0-0 { 174 cmd-dat-pins { 175 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, 176 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, 177 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, 178 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, 179 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, 180 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, 181 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, 182 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, 183 <PINMUX_GPIO167__FUNC_MSDC0_CMD>; 184 input-enable; 185 mediatek,pull-up-adv = <1>; 186 }; 187 clk-pins { 188 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; 189 mediatek,pull-down-adv = <2>; 190 }; 191 rst-pins { 192 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; 193 mediatek,pull-up-adv = <0>; 194 }; 195 }; 196 }; 197 198 mmc0 { 199 pinctrl-0 = <&mmc0_pins_default>; 200 pinctrl-names = "default"; 201 }; 202 }; 203