1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT6779 Pin Controller Device Tree Bindings 8 9maintainers: 10 - Andy Teng <andy.teng@mediatek.com> 11 12description: |+ 13 The pin controller node should be the child of a syscon node with the 14 required property: 15 - compatible: "syscon" 16 17properties: 18 compatible: 19 const: mediatek,mt6779-pinctrl 20 21 reg: 22 minItems: 9 23 maxItems: 9 24 25 reg-names: 26 items: 27 - const: "gpio" 28 - const: "iocfg_rm" 29 - const: "iocfg_br" 30 - const: "iocfg_lm" 31 - const: "iocfg_lb" 32 - const: "iocfg_rt" 33 - const: "iocfg_lt" 34 - const: "iocfg_tl" 35 - const: "eint" 36 37 gpio-controller: true 38 39 "#gpio-cells": 40 const: 2 41 description: | 42 Number of cells in GPIO specifier. Since the generic GPIO 43 binding is used, the amount of cells must be specified as 2. See the below 44 mentioned gpio binding representation for description of particular cells. 45 46 gpio-ranges: 47 minItems: 1 48 maxItems: 5 49 description: | 50 GPIO valid number range. 51 52 interrupt-controller: true 53 54 interrupts: 55 maxItems: 1 56 description: | 57 Specifies the summary IRQ. 58 59 "#interrupt-cells": 60 const: 2 61 62allOf: 63 - $ref: "pinctrl.yaml#" 64 65required: 66 - compatible 67 - reg 68 - reg-names 69 - gpio-controller 70 - "#gpio-cells" 71 - gpio-ranges 72 - interrupt-controller 73 - interrupts 74 - "#interrupt-cells" 75 76patternProperties: 77 '-[0-9]*$': 78 type: object 79 patternProperties: 80 '-pins*$': 81 type: object 82 description: | 83 A pinctrl node should contain at least one subnodes representing the 84 pinctrl groups available on the machine. Each subnode will list the 85 pins it needs, and how they should be configured, with regard to muxer 86 configuration, pullups, drive strength, input enable/disable and input schmitt. 87 $ref: "/schemas/pinctrl/pincfg-node.yaml" 88 89 properties: 90 pinmux: 91 description: 92 integer array, represents gpio pin number and mux setting. 93 Supported pin number and mux varies for different SoCs, and are defined 94 as macros in boot/dts/<soc>-pinfunc.h directly. 95 96 bias-disable: true 97 98 bias-pull-up: true 99 100 bias-pull-down: true 101 102 input-enable: true 103 104 input-disable: true 105 106 output-low: true 107 108 output-high: true 109 110 input-schmitt-enable: true 111 112 input-schmitt-disable: true 113 114 mediatek,pull-up-adv: 115 description: | 116 Pull up setings for 2 pull resistors, R0 and R1. User can 117 configure those special pins. Valid arguments are described as below: 118 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 119 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 120 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 121 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 122 $ref: /schemas/types.yaml#/definitions/uint32 123 enum: [0, 1, 2, 3] 124 125 mediatek,pull-down-adv: 126 description: | 127 Pull down settings for 2 pull resistors, R0 and R1. User can 128 configure those special pins. Valid arguments are described as below: 129 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 130 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 131 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 132 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 133 $ref: /schemas/types.yaml#/definitions/uint32 134 enum: [0, 1, 2, 3] 135 136 required: 137 - pinmux 138 139 additionalProperties: false 140 141additionalProperties: false 142 143examples: 144 - | 145 #include <dt-bindings/interrupt-controller/irq.h> 146 #include <dt-bindings/interrupt-controller/arm-gic.h> 147 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 148 149 soc { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 153 pio: pinctrl@10005000 { 154 compatible = "mediatek,mt6779-pinctrl"; 155 reg = <0 0x10005000 0 0x1000>, 156 <0 0x11c20000 0 0x1000>, 157 <0 0x11d10000 0 0x1000>, 158 <0 0x11e20000 0 0x1000>, 159 <0 0x11e70000 0 0x1000>, 160 <0 0x11ea0000 0 0x1000>, 161 <0 0x11f20000 0 0x1000>, 162 <0 0x11f30000 0 0x1000>, 163 <0 0x1000b000 0 0x1000>; 164 reg-names = "gpio", "iocfg_rm", 165 "iocfg_br", "iocfg_lm", 166 "iocfg_lb", "iocfg_rt", 167 "iocfg_lt", "iocfg_tl", 168 "eint"; 169 gpio-controller; 170 #gpio-cells = <2>; 171 gpio-ranges = <&pio 0 0 210>; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 175 176 mmc0_pins_default: mmc0-0 { 177 cmd-dat-pins { 178 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, 179 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, 180 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, 181 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, 182 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, 183 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, 184 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, 185 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, 186 <PINMUX_GPIO167__FUNC_MSDC0_CMD>; 187 input-enable; 188 mediatek,pull-up-adv = <1>; 189 }; 190 clk-pins { 191 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; 192 mediatek,pull-down-adv = <2>; 193 }; 194 rst-pins { 195 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; 196 mediatek,pull-up-adv = <0>; 197 }; 198 }; 199 }; 200 201 mmc0 { 202 pinctrl-0 = <&mmc0_pins_default>; 203 pinctrl-names = "default"; 204 }; 205 }; 206