1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT6779 Pin Controller 8 9maintainers: 10 - Andy Teng <andy.teng@mediatek.com> 11 - Sean Wang <sean.wang@kernel.org> 12 13description: 14 The MediaTek pin controller on MT6779 is used to control pin 15 functions, pull up/down resistance and drive strength options. 16 17properties: 18 compatible: 19 enum: 20 - mediatek,mt6779-pinctrl 21 - mediatek,mt6797-pinctrl 22 23 reg: 24 description: Physical addresses for GPIO base(s) and EINT registers. 25 26 reg-names: true 27 28 gpio-controller: true 29 30 "#gpio-cells": 31 const: 2 32 description: | 33 Number of cells in GPIO specifier. Since the generic GPIO 34 binding is used, the amount of cells must be specified as 2. See the below 35 mentioned gpio binding representation for description of particular cells. 36 37 gpio-ranges: 38 minItems: 1 39 maxItems: 5 40 description: | 41 GPIO valid number range. 42 43 interrupt-controller: true 44 45 interrupts: 46 maxItems: 1 47 description: | 48 Specifies the summary IRQ. 49 50 "#interrupt-cells": 51 const: 2 52 53required: 54 - compatible 55 - reg 56 - reg-names 57 - gpio-controller 58 - "#gpio-cells" 59 60allOf: 61 - $ref: "pinctrl.yaml#" 62 - if: 63 properties: 64 compatible: 65 contains: 66 const: mediatek,mt6779-pinctrl 67 then: 68 properties: 69 reg: 70 minItems: 9 71 maxItems: 9 72 73 reg-names: 74 items: 75 - const: gpio 76 - const: iocfg_rm 77 - const: iocfg_br 78 - const: iocfg_lm 79 - const: iocfg_lb 80 - const: iocfg_rt 81 - const: iocfg_lt 82 - const: iocfg_tl 83 - const: eint 84 - if: 85 properties: 86 compatible: 87 contains: 88 const: mediatek,mt6797-pinctrl 89 then: 90 properties: 91 reg: 92 minItems: 5 93 maxItems: 5 94 95 reg-names: 96 items: 97 - const: gpio 98 - const: iocfgl 99 - const: iocfgb 100 - const: iocfgr 101 - const: iocfgt 102 - if: 103 properties: 104 reg-names: 105 contains: 106 const: eint 107 then: 108 required: 109 - interrupts 110 - interrupt-controller 111 - "#interrupt-cells" 112 113patternProperties: 114 '-[0-9]*$': 115 type: object 116 additionalProperties: false 117 118 patternProperties: 119 '-pins*$': 120 type: object 121 description: | 122 A pinctrl node should contain at least one subnodes representing the 123 pinctrl groups available on the machine. Each subnode will list the 124 pins it needs, and how they should be configured, with regard to muxer 125 configuration, pullups, drive strength, input enable/disable and input schmitt. 126 $ref: "/schemas/pinctrl/pincfg-node.yaml" 127 128 properties: 129 pinmux: 130 description: 131 integer array, represents gpio pin number and mux setting. 132 Supported pin number and mux varies for different SoCs, and are defined 133 as macros in boot/dts/<soc>-pinfunc.h directly. 134 135 bias-disable: true 136 137 bias-pull-up: true 138 139 bias-pull-down: true 140 141 input-enable: true 142 143 input-disable: true 144 145 output-low: true 146 147 output-high: true 148 149 input-schmitt-enable: true 150 151 input-schmitt-disable: true 152 153 drive-strength: 154 enum: [2, 4, 8, 12, 16] 155 156 slew-rate: 157 enum: [0, 1] 158 159 mediatek,pull-up-adv: 160 description: | 161 Pull up setings for 2 pull resistors, R0 and R1. User can 162 configure those special pins. Valid arguments are described as below: 163 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 164 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 165 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 166 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 167 $ref: /schemas/types.yaml#/definitions/uint32 168 enum: [0, 1, 2, 3] 169 170 mediatek,pull-down-adv: 171 description: | 172 Pull down settings for 2 pull resistors, R0 and R1. User can 173 configure those special pins. Valid arguments are described as below: 174 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 175 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 176 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 177 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 178 $ref: /schemas/types.yaml#/definitions/uint32 179 enum: [0, 1, 2, 3] 180 181 required: 182 - pinmux 183 184 additionalProperties: false 185 186additionalProperties: false 187 188examples: 189 - | 190 #include <dt-bindings/interrupt-controller/irq.h> 191 #include <dt-bindings/interrupt-controller/arm-gic.h> 192 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 193 194 soc { 195 #address-cells = <2>; 196 #size-cells = <2>; 197 198 pio: pinctrl@10005000 { 199 compatible = "mediatek,mt6779-pinctrl"; 200 reg = <0 0x10005000 0 0x1000>, 201 <0 0x11c20000 0 0x1000>, 202 <0 0x11d10000 0 0x1000>, 203 <0 0x11e20000 0 0x1000>, 204 <0 0x11e70000 0 0x1000>, 205 <0 0x11ea0000 0 0x1000>, 206 <0 0x11f20000 0 0x1000>, 207 <0 0x11f30000 0 0x1000>, 208 <0 0x1000b000 0 0x1000>; 209 reg-names = "gpio", "iocfg_rm", 210 "iocfg_br", "iocfg_lm", 211 "iocfg_lb", "iocfg_rt", 212 "iocfg_lt", "iocfg_tl", 213 "eint"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 gpio-ranges = <&pio 0 0 210>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 220 221 mmc0_pins_default: mmc0-0 { 222 cmd-dat-pins { 223 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, 224 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, 225 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, 226 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, 227 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, 228 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, 229 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, 230 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, 231 <PINMUX_GPIO167__FUNC_MSDC0_CMD>; 232 input-enable; 233 mediatek,pull-up-adv = <1>; 234 }; 235 clk-pins { 236 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; 237 mediatek,pull-down-adv = <2>; 238 }; 239 rst-pins { 240 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; 241 mediatek,pull-up-adv = <0>; 242 }; 243 }; 244 }; 245 246 mmc0 { 247 pinctrl-0 = <&mmc0_pins_default>; 248 pinctrl-names = "default"; 249 }; 250 }; 251