xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/intel,pinctrl-thunderbay.yaml (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Thunder Bay pin controller
8
9maintainers:
10  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
11
12description: |
13  Intel Thunder Bay SoC integrates a pin controller which enables control
14  of pin directions, input/output values and configuration
15  for a total of 67 pins.
16
17properties:
18  compatible:
19    const: intel,thunderbay-pinctrl
20
21  reg:
22    maxItems: 1
23
24  gpio-controller: true
25
26  '#gpio-cells':
27    const: 2
28
29  gpio-ranges:
30    maxItems: 1
31
32  interrupts:
33    description:
34      Specifies the interrupt lines to be used by the controller.
35    maxItems: 2
36
37  interrupt-controller: true
38
39  '#interrupt-cells':
40    const: 2
41
42patternProperties:
43  '^gpio@[0-9a-f]*$':
44    type: object
45    additionalProperties: false
46
47    description:
48      Child nodes can be specified to contain pin configuration information,
49      which can then be utilized by pinctrl client devices.
50      The following properties are supported.
51
52    properties:
53      pins:
54        description: |
55          The name(s) of the pins to be configured in the child node.
56          Supported pin names are "GPIO0" up to "GPIO66".
57
58      bias-disable: true
59
60      bias-pull-down: true
61
62      bias-pull-up: true
63
64      drive-strength:
65        description: Drive strength for the pad.
66        enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
67
68      bias-bus-hold:
69        type: boolean
70
71      input-schmitt-enable:
72        type: boolean
73
74      slew-rate:
75        description: GPIO slew rate control.
76                      0 - Slow
77                      1 - Fast
78        enum: [0, 1]
79
80additionalProperties: false
81
82required:
83  - compatible
84  - reg
85  - gpio-controller
86  - '#gpio-cells'
87  - gpio-ranges
88  - interrupts
89  - interrupt-controller
90  - '#interrupt-cells'
91
92examples:
93  - |
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95    #include <dt-bindings/interrupt-controller/irq.h>
96    // Example 1
97    pinctrl0: gpio@0 {
98        compatible = "intel,thunderbay-pinctrl";
99        reg = <0x600b0000 0x88>;
100        gpio-controller;
101        #gpio-cells = <0x2>;
102        gpio-ranges = <&pinctrl0 0 0 67>;
103        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
104                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
105        interrupt-controller;
106        #interrupt-cells = <2>;
107    };
108
109    // Example 2
110    pinctrl1: gpio@1 {
111        compatible = "intel,thunderbay-pinctrl";
112        reg = <0x600c0000 0x88>;
113        gpio-controller;
114        #gpio-cells = <0x2>;
115        gpio-ranges = <&pinctrl1 0 0 53>;
116        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
117                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
118        interrupt-controller;
119        #interrupt-cells = <2>;
120    };
121