xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/intel,pinctrl-keembay.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Keem Bay pin controller Device Tree Bindings
8
9maintainers:
10  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
11
12description: |
13  Intel Keem Bay SoC integrates a pin controller which enables control
14  of pin directions, input/output values and configuration
15  for a total of 80 pins.
16
17properties:
18  compatible:
19    const: intel,keembay-pinctrl
20
21  reg:
22    maxItems: 2
23
24  gpio-controller: true
25
26  '#gpio-cells':
27    const: 2
28
29  ngpios:
30    description: The number of GPIOs exposed.
31    const: 80
32
33  interrupts:
34    description:
35      Specifies the interrupt lines to be used by the controller.
36      Each interrupt line is shared by upto 4 GPIO lines.
37    maxItems: 8
38
39  interrupt-controller: true
40
41  '#interrupt-cells':
42    const: 2
43
44patternProperties:
45  '^gpio@[0-9a-f]*$':
46    type: object
47
48    description:
49      Child nodes can be specified to contain pin configuration information,
50      which can then be utilized by pinctrl client devices.
51      The following properties are supported.
52
53    properties:
54      pins:
55        description: |
56          The name(s) of the pins to be configured in the child node.
57          Supported pin names are "GPIO0" up to "GPIO79".
58
59      bias-disable: true
60
61      bias-pull-down: true
62
63      bias-pull-up: true
64
65      drive-strength:
66        description: IO pads drive strength in milli Ampere.
67        enum: [2, 4, 8, 12]
68
69      bias-bus-hold:
70        type: boolean
71
72      input-schmitt-enable:
73        type: boolean
74
75      slew-rate:
76        description: GPIO slew rate control.
77                      0 - Fast(~100MHz)
78                      1 - Slow(~50MHz)
79        enum: [0, 1]
80
81additionalProperties: false
82
83required:
84  - compatible
85  - reg
86  - gpio-controller
87  - ngpios
88  - '#gpio-cells'
89  - interrupts
90  - interrupt-controller
91  - '#interrupt-cells'
92
93examples:
94  - |
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96    #include <dt-bindings/interrupt-controller/irq.h>
97    // Example 1
98    gpio@0 {
99        compatible = "intel,keembay-pinctrl";
100        reg = <0x600b0000 0x88>,
101              <0x600b0190 0x1ac>;
102        gpio-controller;
103        ngpios = <0x50>;
104        #gpio-cells = <0x2>;
105        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
113        interrupt-controller;
114        #interrupt-cells = <2>;
115    };
116
117    // Example 2
118    gpio@1 {
119        compatible = "intel,keembay-pinctrl";
120        reg = <0x600c0000 0x88>,
121              <0x600c0190 0x1ac>;
122        gpio-controller;
123        ngpios = <0x50>;
124        #gpio-cells = <0x2>;
125        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
126                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
127                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
128                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
129                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
130                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
131                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
132                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
133        interrupt-controller;
134        #interrupt-cells = <2>;
135    };
136