1Imagination Technologies Pistachio SoC pin controllers 2====================================================== 3 4The pin controllers on Pistachio are a combined GPIO controller, (GPIO) 5interrupt controller, and pinmux + pinconf device. The system ("east") pin 6controller on Pistachio has 99 pins, 90 of which are MFIOs which can be 7configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs 8each. The GPIO banks are represented as sub-nodes of the pad controller node. 9 10Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and 11../interrupt-controller/interrupts.txt for generic information regarding 12pin controller, GPIO, and interrupt bindings. 13 14Required properties for pin controller node: 15-------------------------------------------- 16 - compatible: "img,pistachio-system-pinctrl". 17 - reg: Address range of the pinctrl registers. 18 19Required properties for GPIO bank sub-nodes: 20-------------------------------------------- 21 - interrupts: Interrupt line for the GPIO bank. 22 - gpio-controller: Indicates the device is a GPIO controller. 23 - #gpio-cells: Must be two. The first cell is the GPIO pin number and the 24 second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for 25 a list of possible values. 26 - interrupt-controller: Indicates the device is an interrupt controller. 27 - #interrupt-cells: Must be two. The first cell is the GPIO pin number and 28 the second cell encodes the interrupt flags. See 29 <dt-bindings/interrupt-controller/irq.h> for a list of valid flags. 30 31Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. 32 33Required properties for pin configuration sub-nodes: 34---------------------------------------------------- 35 - pins: List of pins to which the configuration applies. See below for a 36 list of possible pins. 37 38Optional properties for pin configuration sub-nodes: 39---------------------------------------------------- 40 - function: Mux function for the specified pins. This is not applicable for 41 non-MFIO pins. See below for a list of valid functions for each pin. 42 - bias-high-impedance: Enable high-impedance mode. 43 - bias-pull-up: Enable weak pull-up. 44 - bias-pull-down: Enable weak pull-down. 45 - bias-bus-hold: Enable bus-keeper mode. 46 - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. 47 - input-schmitt-enable: Enable Schmitt trigger. 48 - input-schmitt-disable: Disable Schmitt trigger. 49 - slew-rate: Slew rate control. 0 for slow, 1 for fast. 50 51Pin Functions 52--- --------- 53mfio0 spim1 54mfio1 spim1, spim0, uart1 55mfio2 spim1, spim0, uart1 56mfio3 spim1 57mfio4 spim1 58mfio5 spim1 59mfio6 spim1 60mfio7 spim1 61mfio8 spim0 62mfio9 spim0 63mfio10 spim0 64mfio11 spis 65mfio12 spis 66mfio13 spis 67mfio14 spis 68mfio15 sdhost, mips_trace_clk, mips_trace_data 69mfio16 sdhost, mips_trace_dint, mips_trace_data 70mfio17 sdhost, mips_trace_trigout, mips_trace_data 71mfio18 sdhost, mips_trace_trigin, mips_trace_data 72mfio19 sdhost, mips_trace_dm, mips_trace_data 73mfio20 sdhost, mips_trace_probe_n, mips_trace_data 74mfio21 sdhost, mips_trace_data 75mfio22 sdhost, mips_trace_data 76mfio23 sdhost 77mfio24 sdhost 78mfio25 sdhost 79mfio26 sdhost 80mfio27 sdhost 81mfio28 i2c0, spim0 82mfio29 i2c0, spim0 83mfio30 i2c1, spim0 84mfio31 i2c1, spim1 85mfio32 i2c2 86mfio33 i2c2 87mfio34 i2c3 88mfio35 i2c3 89mfio36 i2s_out, audio_clk_in 90mfio37 i2s_out, debug_raw_cca_ind 91mfio38 i2s_out, debug_ed_sec20_cca_ind 92mfio39 i2s_out, debug_ed_sec40_cca_ind 93mfio40 i2s_out, debug_agc_done_0 94mfio41 i2s_out, debug_agc_done_1 95mfio42 i2s_out, debug_ed_cca_ind 96mfio43 i2s_out, debug_s2l_done 97mfio44 i2s_out 98mfio45 i2s_dac_clk, audio_sync 99mfio46 audio_trigger 100mfio47 i2s_in 101mfio48 i2s_in 102mfio49 i2s_in 103mfio50 i2s_in 104mfio51 i2s_in 105mfio52 i2s_in 106mfio53 i2s_in 107mfio54 i2s_in, spdif_in 108mfio55 uart0, spim0, spim1 109mfio56 uart0, spim0, spim1 110mfio57 uart0, spim0, spim1 111mfio58 uart0, spim1 112mfio59 uart1 113mfio60 uart1 114mfio61 spdif_out 115mfio62 spdif_in 116mfio63 eth, mips_trace_clk, mips_trace_data 117mfio64 eth, mips_trace_dint, mips_trace_data 118mfio65 eth, mips_trace_trigout, mips_trace_data 119mfio66 eth, mips_trace_trigin, mips_trace_data 120mfio67 eth, mips_trace_dm, mips_trace_data 121mfio68 eth, mips_trace_probe_n, mips_trace_data 122mfio69 eth, mips_trace_data 123mfio70 eth, mips_trace_data 124mfio71 eth 125mfio72 ir 126mfio73 pwmpdm, mips_trace_clk, sram_debug 127mfio74 pwmpdm, mips_trace_dint, sram_debug 128mfio75 pwmpdm, mips_trace_trigout, rom_debug 129mfio76 pwmpdm, mips_trace_trigin, rom_debug 130mfio77 mdc_debug, mips_trace_dm, rpu_debug 131mfio78 mdc_debug, mips_trace_probe_n, rpu_debug 132mfio79 ddr_debug, mips_trace_data, mips_debug 133mfio80 ddr_debug, mips_trace_data, mips_debug 134mfio81 dreq0, mips_trace_data, eth_debug 135mfio82 dreq1, mips_trace_data, eth_debug 136mfio83 mips_pll_lock, mips_trace_data, usb_debug 137mfio84 audio_pll_lock, mips_trace_data, usb_debug 138mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug 139mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug 140mfio87 sys_pll_lock, dreq2, socif_debug 141mfio88 wifi_pll_lock, dreq3, socif_debug 142mfio89 bt_pll_lock, dreq4, dreq5 143tck 144trstn 145tdi 146tms 147tdo 148jtag_comply 149safe_mode 150por_disable 151resetn 152 153Example: 154-------- 155pinctrl@18101c00 { 156 compatible = "img,pistachio-system-pinctrl"; 157 reg = <0x18101C00 0x400>; 158 159 gpio0: gpio0 { 160 interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>; 161 162 gpio-controller; 163 #gpio-cells = <2>; 164 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 }; 168 169 ... 170 171 gpio5: gpio5 { 172 interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>; 173 174 gpio-controller; 175 #gpio-cells = <2>; 176 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 }; 180 181 ... 182 183 uart0_xfer: uart0-xfer { 184 uart0-rxd { 185 pins = "mfio55"; 186 function = "uart0"; 187 }; 188 uart0-txd { 189 pins = "mfio56"; 190 function = "uart0"; 191 }; 192 }; 193 194 uart0_rts_cts: uart0-rts-cts { 195 uart0-rts { 196 pins = "mfio57"; 197 function = "uart0"; 198 }; 199 uart0-cts { 200 pins = "mfio58"; 201 function = "uart0"; 202 }; 203 }; 204}; 205 206uart@... { 207 ... 208 pinctrl-names = "default"; 209 pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; 210 ... 211}; 212 213usb_vbus: fixed-regulator { 214 ... 215 gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; 216 ... 217}; 218