1* Freescale IOMUX Controller (IOMUXC) for i.MX 2 3The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC 4to share one PAD to several functional blocks. The sharing is done by 5multiplexing the PAD input/output signals. For each PAD there are up to 68 muxing options (called ALT modes). Since different modules require 7different PAD settings (like pull up, keeper, etc) the IOMUXC controls 8also the PAD settings parameters. 9 10Please refer to pinctrl-bindings.txt in this directory for details of the 11common pinctrl bindings used by client devices, including the meaning of the 12phrase "pin configuration node". 13 14Freescale IMX pin configuration node is a node of a group of pins which can be 15used for a specific device or function. This node represents both mux and config 16of the pins in that group. The 'mux' selects the function mode(also named mux 17mode) this pin can work on and the 'config' configures various pad settings 18such as pull-up, open drain, drive strength, etc. 19 20Required properties for iomux controller: 21- compatible: "fsl,<soc>-iomuxc" 22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. 23 24Required properties for pin configuration node: 25- fsl,pins: each entry consists of 6 integers and represents the mux and config 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 27 input_val> are specified using a PIN_FUNC_ID macro, which can be found in 28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is 29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry 30 looks like <PIN_FUNC_ID CONFIG> in the example below. 31 32Bits used for CONFIG: 33NO_PAD_CTL(1 << 31): indicate this pin does not need config. 34 35SION(1 << 30): Software Input On Field. 36Force the selected mux mode input path no matter of MUX_MODE functionality. 37By default the input path is determined by functionality of the selected 38mux mode (regular). 39 40Other bits are used for PAD setting. 41Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part 42of bits definitions. 43 44NOTE: 45Some requirements for using fsl,imx-pinctrl binding: 461. We have pin function node defined under iomux controller node to represent 47 what pinmux functions this SoC supports. 482. The pin configuration node intends to work on a specific function should 49 to be defined under that specific function node. 50 The function node's name should represent well about what function 51 this group of pins in this pin configuration node are working on. 523. The driver can use the function node's name and pin configuration node's 53 name describe the pin function and group hierarchy. 54 For example, Linux IMX pinctrl driver takes the function node's name 55 as the function name and pin configuration node's name as group name to 56 create the map table. 574. Each pin configuration node should have a phandle, devices can set pins 58 configurations by referring to the phandle of that pin configuration node. 59 60Examples: 61usdhc@219c000 { /* uSDHC4 */ 62 non-removable; 63 vmmc-supply = <®_3p3v>; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_usdhc4_1>; 66}; 67 68iomuxc@20e0000 { 69 compatible = "fsl,imx6q-iomuxc"; 70 reg = <0x020e0000 0x4000>; 71 72 /* shared pinctrl settings */ 73 usdhc4 { 74 pinctrl_usdhc4_1: usdhc4grp-1 { 75 fsl,pins = < 76 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 77 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 78 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 79 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 80 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 81 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 82 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 83 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 84 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 85 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 86 >; 87 }; 88 .... 89}; 90Refer to the IOMUXC controller chapter in imx6q datasheet, 910x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, 9280Ohm driver strength and Fast Slew Rate. 93User should refer to each SoC spec to set the correct value. 94