1Broadcom Northstar pins mux controller 2 3Some of Northstar SoCs's pins can be used for various purposes thanks to the mux 4controller. This binding allows describing mux controller and listing available 5functions. They can be referenced later by other bindings to let system 6configure controller correctly. 7 8A list of pins varies across chipsets so few bindings are available. 9 10Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" 11noce. 12 13Required properties: 14- compatible: must be one of: 15 "brcm,bcm4708-pinmux" 16 "brcm,bcm4709-pinmux" 17 "brcm,bcm53012-pinmux" 18- offset: offset of pin registers in the CRU block 19 20Functions and their groups available for all chipsets: 21- "spi": "spi_grp" 22- "i2c": "i2c_grp" 23- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" 24- "uart1": "uart1_grp" 25 26Additionally available on BCM4709 and BCM53012: 27- "mdio": "mdio_grp" 28- "uart2": "uart2_grp" 29- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp" 30 31For documentation of subnodes see: 32Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 33 34Example: 35 dmu@1800c000 { 36 compatible = "simple-bus"; 37 ranges = <0 0x1800c000 0x1000>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 cru@100 { 42 compatible = "syscon", "simple-mfd"; 43 reg = <0x100 0x1a4>; 44 45 pinctrl { 46 compatible = "brcm,bcm4708-pinmux"; 47 offset = <0xc0>; 48 49 spi-pins { 50 function = "spi"; 51 groups = "spi_grp"; 52 }; 53 }; 54 }; 55 }; 56