1Axis ARTPEC-6 Pin Controller 2 3Required properties: 4- compatible: "axis,artpec6-pinctrl". 5- reg: Should contain the register physical address and length for the pin 6 controller. 7 8A pinctrl node should contain at least one subnode representing the pinctrl 9groups available on the machine. Each subnode will list the mux function 10required and what pin group it will use. Each subnode will also configure the 11drive strength and bias pullup of the pin group. If either of these options is 12not set, its actual value will be unspecified. 13 14 15Required subnode-properties: 16- function: Function to mux. 17- groups: Name of the pin group to use for the function above. 18 19 Available functions and groups (function: group0, group1...): 20 gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, 21 i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, 22 spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, 23 uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, 24 uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, 25 uart5nocts 26 cpuclkout: cpuclkoutgrp0 27 udlclkout: udlclkoutgrp0 28 i2c1: i2c1grp0 29 i2c2: i2c2grp0 30 i2c3: i2c3grp0 31 i2s0: i2s0grp0 32 i2s1: i2s1grp0 33 i2srefclk: i2srefclkgrp0 34 spi0: spi0grp0 35 spi1: spi1grp0 36 pciedebug: pciedebuggrp0 37 uart0: uart0grp0, uart0grp1, uart0grp2 38 uart1: uart1grp0, uart1grp1 39 uart2: uart2grp0, uart2grp1, uart2grp2 40 uart3: uart3grp0 41 uart4: uart4grp0, uart4grp1 42 uart5: uart5grp0, uart5grp1, uart5nocts 43 nand: nandgrp0 44 sdio0: sdio0grp0 45 sdio1: sdio1grp0 46 ethernet: ethernetgrp0 47 48 49Optional subnode-properties (see pinctrl-bindings.txt): 50- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3. 51- bias-pull-up 52- bias-disable 53 54Examples: 55pinctrl@f801d000 { 56 compatible = "axis,artpec6-pinctrl"; 57 reg = <0xf801d000 0x400>; 58 59 pinctrl_uart0: uart0grp { 60 function = "uart0"; 61 groups = "uart0grp0"; 62 drive-strength = <4>; 63 bias-pull-up; 64 }; 65 pinctrl_uart3: uart3grp { 66 function = "uart3"; 67 groups = "uart3grp0"; 68 }; 69}; 70uart0: uart@f8036000 { 71 compatible = "arm,pl011", "arm,primecell"; 72 reg = <0xf8036000 0x1000>; 73 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 74 clocks = <&pll2div24>, <&apb_pclk>; 75 clock-names = "uart_clk", "apb_pclk"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_uart0>; 78}; 79uart3: uart@f8039000 { 80 compatible = "arm,pl011", "arm,primecell"; 81 reg = <0xf8039000 0x1000>; 82 interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&pll2div24>, <&apb_pclk>; 84 clock-names = "uart_clk", "apb_pclk"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_uart3>; 87}; 88