1* Atmel AT91 Pinmux Controller 2 3The AT91 Pinmux Controller, enables the IC 4to share one PAD to several functional blocks. The sharing is done by 5multiplexing the PAD input/output signals. For each PAD there are up to 68 muxing options (called periph modes). Since different modules require 7different PAD settings (like pull up, keeper, etc) the controller controls 8also the PAD settings parameters. 9 10Please refer to pinctrl-bindings.txt in this directory for details of the 11common pinctrl bindings used by client devices, including the meaning of the 12phrase "pin configuration node". 13 14Atmel AT91 pin configuration node is a node of a group of pins which can be 15used for a specific device or function. This node represents both mux and config 16of the pins in that group. The 'pins' selects the function mode(also named pin 17mode) this pin can work on and the 'config' configures various pad settings 18such as pull-up, multi drive, etc. 19 20Required properties for iomux controller: 21- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" 22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" 23 or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl" 24- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be 25 configured in this periph mode. All the periph and bank need to be describe. 26 27How to create such array: 28 29Each column will represent the possible peripheral of the pinctrl 30Each line will represent a pio bank 31 32Take an example on the 9260 33Peripheral: 2 ( A and B) 34Bank: 3 (A, B and C) 35=> 36 37 /* A B */ 38 0xffffffff 0xffc00c3b /* pioA */ 39 0xffffffff 0x7fff3ccf /* pioB */ 40 0xffffffff 0x007fffff /* pioC */ 41 42For each peripheral/bank we will describe in a u32 if a pin can be 43configured in it by putting 1 to the pin bit (1 << pin) 44 45Let's take the pioA on peripheral B 46From the datasheet Table 10-2. 47Peripheral B 48PA0 MCDB0 49PA1 MCCDB 50PA2 51PA3 MCDB3 52PA4 MCDB2 53PA5 MCDB1 54PA6 55PA7 56PA8 57PA9 58PA10 ETX2 59PA11 ETX3 60PA12 61PA13 62PA14 63PA15 64PA16 65PA17 66PA18 67PA19 68PA20 69PA21 70PA22 ETXER 71PA23 ETX2 72PA24 ETX3 73PA25 ERX2 74PA26 ERX3 75PA27 ERXCK 76PA28 ECRS 77PA29 ECOL 78PA30 RXD4 79PA31 TXD4 80 81=> 0xffc00c3b 82 83Required properties for pin configuration node: 84- atmel,pins: 4 integers array, represents a group of pins mux and config 85 setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. 86 The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... 87 PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... 88 89Bits used for CONFIG: 90PULL_UP (1 << 0): indicate this pin needs a pull up. 91MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive. 92 Multi-drive is equivalent to open-drain type output. 93DEGLITCH (1 << 2): indicate this pin needs deglitch. 94PULL_DOWN (1 << 3): indicate this pin needs a pull down. 95DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger. 96DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the 97 following values: 98 00 - No change (reset state value kept) 99 01 - Low 100 10 - Medium 101 11 - High 102OUTPUT (1 << 7): indicate this pin need to be configured as an output. 103OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low) 104SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable 105DEBOUNCE (1 << 16): indicate this pin needs debounce. 106DEBOUNCE_VAL (0x3fff << 17): debounce value. 107 108NOTE: 109Some requirements for using atmel,at91rm9200-pinctrl binding: 1101. We have pin function node defined under at91 controller node to represent 111 what pinmux functions this SoC supports. 1122. The driver can use the function node's name and pin configuration node's 113 name describe the pin function and group hierarchy. 114 For example, Linux at91 pinctrl driver takes the function node's name 115 as the function name and pin configuration node's name as group name to 116 create the map table. 1173. Each pin configuration node should have a phandle, devices can set pins 118 configurations by referring to the phandle of that pin configuration node. 1194. The gpio controller must be describe in the pinctrl simple-bus. 120 121For each bank the required properties are: 122- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or 123 "microchip,sam9x60-gpio" 124 or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio" 125- reg: physical base address and length of the controller's registers 126- interrupts: interrupt outputs from the controller 127- interrupt-controller: marks the device node as an interrupt controller 128- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt 129 for more details. 130- gpio-controller 131- #gpio-cells: should be 2; the first cell is the GPIO number and the second 132 cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>. 133- clocks: bank clock 134 135Examples: 136 137pinctrl@fffff400 { 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges; 141 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 142 reg = <0xfffff400 0x600>; 143 144 pioA: gpio@fffff400 { 145 compatible = "atmel,at91sam9x5-gpio"; 146 reg = <0xfffff400 0x200>; 147 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 148 #gpio-cells = <2>; 149 gpio-controller; 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 153 }; 154 155 atmel,mux-mask = < 156 /* A B */ 157 0xffffffff 0xffc00c3b /* pioA */ 158 0xffffffff 0x7fff3ccf /* pioB */ 159 0xffffffff 0x007fffff /* pioC */ 160 >; 161 162 /* shared pinctrl settings */ 163 dbgu { 164 pinctrl_dbgu: dbgu-0 { 165 atmel,pins = 166 <1 14 0x1 0x0 /* PB14 periph A */ 167 1 15 0x1 0x1>; /* PB15 periph A with pullup */ 168 }; 169 }; 170}; 171 172dbgu: serial@fffff200 { 173 compatible = "atmel,at91sam9260-usart"; 174 reg = <0xfffff200 0x200>; 175 interrupts = <1 4 7>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_dbgu>; 178}; 179