1TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs 2 3OMAP CONTROL PHY 4 5Required properties: 6 - compatible: Should be one of 7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4. 8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register 9 e.g. USB2_PHY on OMAP5. 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control 11 e.g. USB3 PHY and SATA PHY on OMAP5. 12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to 13 set PCS delay value. 14 e.g. PCIE PHY in DRA7x 15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on 16 DRA7 platform. 17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on 18 AM437 platform. 19 - reg : register ranges as listed in the reg-names property 20 - reg-names: "otghs_control" for control-phy-otghs 21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie 22 "power" for all other types 23 24omap_control_usb: omap-control-usb@4a002300 { 25 compatible = "ti,control-phy-otghs"; 26 reg = <0x4a00233c 0x4>; 27 reg-names = "otghs_control"; 28}; 29 30OMAP USB2 PHY 31 32Required properties: 33 - compatible: Should be "ti,omap-usb2" 34 Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on 35 DRA7x 36 Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY 37 in DRA7x 38 Should be "ti,am654-usb2" for the USB2 PHYs on AM654. 39 - reg : Address and length of the register set for the device. 40 - #phy-cells: determine the number of cells that should be given in the 41 phandle while referencing this phy. 42 - clocks: a list of phandles and clock-specifier pairs, one for each entry in 43 clock-names. 44 - clock-names: should include: 45 * "wkupclk" - wakeup clock. 46 * "refclk" - reference clock (optional). 47 48Deprecated properties: 49 - ctrl-module : phandle of the control module used by PHY driver to power on 50 the PHY. 51 52Recommended properies: 53- syscon-phy-power : phandle/offset pair. Phandle to the system control 54 module and the register offset to power on/off the PHY. 55 56This is usually a subnode of ocp2scp to which it is connected. 57 58usb2phy@4a0ad080 { 59 compatible = "ti,omap-usb2"; 60 reg = <0x4a0ad080 0x58>; 61 ctrl-module = <&omap_control_usb>; 62 #phy-cells = <0>; 63 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; 64 clock-names = "wkupclk", "refclk"; 65}; 66 67TI PIPE3 PHY 68 69Required properties: 70 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or 71 "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated. 72 - reg : Address and length of the register set for the device. 73 - reg-names: The names of the register addresses corresponding to the registers 74 filled in "reg". 75 - #phy-cells: determine the number of cells that should be given in the 76 phandle while referencing this phy. 77 - clocks: a list of phandles and clock-specifier pairs, one for each entry in 78 clock-names. 79 - clock-names: should include: 80 * "wkupclk" - wakeup clock. 81 * "sysclk" - system clock. 82 * "refclk" - reference clock. 83 * "dpll_ref" - external dpll ref clk 84 * "dpll_ref_m2" - external dpll ref clk 85 * "phy-div" - divider for apll 86 * "div-clk" - apll clock 87 88Optional properties: 89 - id: If there are multiple instance of the same type, in order to 90 differentiate between each instance "id" can be used (e.g., multi-lane PCIe 91 PHY). If "id" is not provided, it is set to default value of '1'. 92 - syscon-pllreset: Handle to system control region that contains the 93 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 94 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. 95 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the 96 register offset to write the PCS delay value. 97 98Deprecated properties: 99 - ctrl-module : phandle of the control module used by PHY driver to power on 100 the PHY. 101 102Recommended properies: 103 - syscon-phy-power : phandle/offset pair. Phandle to the system control 104 module and the register offset to power on/off the PHY. 105 106This is usually a subnode of ocp2scp to which it is connected. 107 108usb3phy@4a084400 { 109 compatible = "ti,phy-usb3"; 110 reg = <0x4a084400 0x80>, 111 <0x4a084800 0x64>, 112 <0x4a084c00 0x40>; 113 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 114 ctrl-module = <&omap_control_usb>; 115 #phy-cells = <0>; 116 clocks = <&usb_phy_cm_clk32k>, 117 <&sys_clkin>, 118 <&usb_otg_ss_refclk960m>; 119 clock-names = "wkupclk", 120 "sysclk", 121 "refclk"; 122}; 123 124sata_phy: phy@4a096000 { 125 compatible = "ti,phy-pipe3-sata"; 126 reg = <0x4A096000 0x80>, /* phy_rx */ 127 <0x4A096400 0x64>, /* phy_tx */ 128 <0x4A096800 0x40>; /* pll_ctrl */ 129 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 130 ctrl-module = <&omap_control_sata>; 131 clocks = <&sys_clkin1>, <&sata_ref_clk>; 132 clock-names = "sysclk", "refclk"; 133 syscon-pllreset = <&scm_conf 0x3fc>; 134 #phy-cells = <0>; 135}; 136