1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: TI J721E WIZ (SERDES Wrapper) 9 10maintainers: 11 - Kishon Vijay Abraham I <kishon@ti.com> 12 13properties: 14 compatible: 15 enum: 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 19 power-domains: 20 maxItems: 1 21 22 clocks: 23 maxItems: 3 24 description: clock-specifier to represent input to the WIZ 25 26 clock-names: 27 items: 28 - const: fck 29 - const: core_ref_clk 30 - const: ext_ref_clk 31 32 num-lanes: 33 minimum: 1 34 maximum: 4 35 36 "#address-cells": 37 const: 1 38 39 "#size-cells": 40 const: 1 41 42 "#reset-cells": 43 const: 1 44 45 ranges: true 46 47 assigned-clocks: 48 minItems: 1 49 maxItems: 2 50 51 assigned-clock-parents: 52 minItems: 1 53 maxItems: 2 54 55 assigned-clock-rates: 56 minItems: 1 57 maxItems: 2 58 59 typec-dir-gpios: 60 maxItems: 1 61 description: 62 GPIO to signal Type-C cable orientation for lane swap. 63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 64 achieve the funtionality of an external type-C plug flip mux. 65 66 typec-dir-debounce-ms: 67 minimum: 100 68 maximum: 1000 69 default: 100 70 description: 71 Number of milliseconds to wait before sampling typec-dir-gpio. 72 If not specified, the default debounce of 100ms will be used. 73 Type-C spec states minimum CC pin debounce of 100 ms and maximum 74 of 200 ms. However, some solutions might need more than 200 ms. 75 76patternProperties: 77 "^pll[0|1]-refclk$": 78 type: object 79 description: | 80 WIZ node should have subnodes for each of the PLLs present in 81 the SERDES. 82 properties: 83 clocks: 84 maxItems: 2 85 description: Phandle to clock nodes representing the two inputs to PLL. 86 87 "#clock-cells": 88 const: 0 89 90 assigned-clocks: 91 maxItems: 1 92 93 assigned-clock-parents: 94 maxItems: 1 95 96 required: 97 - clocks 98 - "#clock-cells" 99 - assigned-clocks 100 - assigned-clock-parents 101 102 "^cmn-refclk1?-dig-div$": 103 type: object 104 description: 105 WIZ node should have subnodes for each of the PMA common refclock 106 provided by the SERDES. 107 properties: 108 clocks: 109 maxItems: 1 110 description: Phandle to the clock node representing the input to the 111 divider clock. 112 113 "#clock-cells": 114 const: 0 115 116 required: 117 - clocks 118 - "#clock-cells" 119 120 "^refclk-dig$": 121 type: object 122 description: | 123 WIZ node should have subnode for refclk_dig to select the reference 124 clock source for the reference clock used in the PHY and PMA digital 125 logic. 126 properties: 127 clocks: 128 minItems: 2 129 maxItems: 4 130 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing 131 the inputs to refclk_dig 132 133 "#clock-cells": 134 const: 0 135 136 assigned-clocks: 137 maxItems: 1 138 139 assigned-clock-parents: 140 maxItems: 1 141 142 required: 143 - clocks 144 - "#clock-cells" 145 - assigned-clocks 146 - assigned-clock-parents 147 148 "^serdes@[0-9a-f]+$": 149 type: object 150 description: | 151 WIZ node should have '1' subnode for the SERDES. It could be either 152 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the 153 bindings specified in 154 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt 155 Torrent SERDES should follow the bindings specified in 156 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml 157 158required: 159 - compatible 160 - power-domains 161 - clocks 162 - clock-names 163 - num-lanes 164 - "#address-cells" 165 - "#size-cells" 166 - "#reset-cells" 167 - ranges 168 169additionalProperties: false 170 171examples: 172 - | 173 #include <dt-bindings/soc/ti,sci_pm_domain.h> 174 175 wiz@5000000 { 176 compatible = "ti,j721e-wiz-16g"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 180 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 181 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 183 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 184 num-lanes = <2>; 185 #reset-cells = <1>; 186 ranges = <0x5000000 0x5000000 0x10000>; 187 188 pll0-refclk { 189 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 190 #clock-cells = <0>; 191 assigned-clocks = <&wiz1_pll0_refclk>; 192 assigned-clock-parents = <&k3_clks 293 13>; 193 }; 194 195 pll1-refclk { 196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 197 #clock-cells = <0>; 198 assigned-clocks = <&wiz1_pll1_refclk>; 199 assigned-clock-parents = <&k3_clks 293 0>; 200 }; 201 202 cmn-refclk-dig-div { 203 clocks = <&wiz1_refclk_dig>; 204 #clock-cells = <0>; 205 }; 206 207 cmn-refclk1-dig-div { 208 clocks = <&wiz1_pll1_refclk>; 209 #clock-cells = <0>; 210 }; 211 212 refclk-dig { 213 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, 214 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 215 #clock-cells = <0>; 216 assigned-clocks = <&wiz0_refclk_dig>; 217 assigned-clock-parents = <&k3_clks 292 11>; 218 }; 219 220 serdes@5000000 { 221 compatible = "cdns,ti,sierra-phy-t0"; 222 reg-names = "serdes"; 223 reg = <0x5000000 0x10000>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 resets = <&serdes_wiz0 0>; 227 reset-names = "sierra_reset"; 228 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 229 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 230 }; 231 }; 232