xref: /freebsd/sys/contrib/device-tree/Bindings/phy/ti,phy-gmii-sel.yaml (revision dd41de95a84d979615a2ef11df6850622bf6184e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: CPSW Port's Interface Mode Selection PHY Tree Bindings
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13description: |
14  TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15  two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16  The interface mode is selected by configuring the MII mode selection register(s)
17  (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18  bit fields placement in SCM are different between SoCs while fields meaning
19  is the same.
20                                               +--------------+
21        +-------------------------------+      |SCM           |
22        |                     CPSW      |      |  +---------+ |
23        |        +--------------------------------+gmii_sel | |
24        |        |                      |      |  +---------+ |
25        |   +----v---+     +--------+   |      +--------------+
26        |   |Port 1..<--+-->GMII/MII<------->
27        |   |        |  |  |        |   |
28        |   +--------+  |  +--------+   |
29        |               |               |
30        |               |  +--------+   |
31        |               |  | RMII   <------->
32        |               +-->        |   |
33        |               |  +--------+   |
34        |               |               |
35        |               |  +--------+   |
36        |               |  | RGMII  <------->
37        |               +-->        |   |
38        |                  +--------+   |
39        +-------------------------------+
40
41  CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42  CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
43  |
44  CPSW Port's Interface Mode Selection PHY device should defined as child device
45  of SCM node (scm_conf) and can be attached to each CPSW port node using standard
46  PHY bindings.
47
48properties:
49  compatible:
50    enum:
51      - ti,am3352-phy-gmii-sel
52      - ti,dra7xx-phy-gmii-sel
53      - ti,am43xx-phy-gmii-sel
54      - ti,dm814-phy-gmii-sel
55      - ti,am654-phy-gmii-sel
56
57  reg:
58    description: Address and length of the register set for the device
59
60  '#phy-cells': true
61
62allOf:
63  - if:
64      properties:
65        compatible:
66          contains:
67            enum:
68              - ti,dra7xx-phy-gmii-sel
69              - ti,dm814-phy-gmii-sel
70              - ti,am654-phy-gmii-sel
71    then:
72      properties:
73        '#phy-cells':
74          const: 1
75          description: CPSW port number (starting from 1)
76  - if:
77      properties:
78        compatible:
79          contains:
80            enum:
81              - ti,am3352-phy-gmii-sel
82              - ti,am43xx-phy-gmii-sel
83    then:
84      properties:
85        '#phy-cells':
86          const: 2
87          description: |
88            - CPSW port number (starting from 1)
89            - RMII refclk mode
90
91required:
92  - compatible
93  - reg
94  - '#phy-cells'
95
96additionalProperties: false
97
98examples:
99  - |
100    phy_gmii_sel: phy-gmii-sel@650 {
101        compatible = "ti,am3352-phy-gmii-sel";
102        reg = <0x650 0x4>;
103        #phy-cells = <2>;
104    };
105