xref: /freebsd/sys/contrib/device-tree/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9description: |
10  This describes the devicetree bindings for PHY interfaces built into
11  USB3 controller implemented on Socionext UniPhier SoCs.
12  Although the controller includes High-Speed PHY and Super-Speed PHY,
13  this describes about High-Speed PHY.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19  compatible:
20    enum:
21      - socionext,uniphier-pro5-usb3-hsphy
22      - socionext,uniphier-pxs2-usb3-hsphy
23      - socionext,uniphier-ld20-usb3-hsphy
24      - socionext,uniphier-pxs3-usb3-hsphy
25      - socionext,uniphier-nx1-usb3-hsphy
26
27  reg:
28    maxItems: 1
29
30  "#phy-cells":
31    const: 0
32
33  clocks:
34    minItems: 2
35    maxItems: 3
36
37  clock-names: true
38
39  resets:
40    maxItems: 2
41
42  reset-names: true
43
44  vbus-supply:
45    description: A phandle to the regulator for USB VBUS
46
47  nvmem-cells:
48    maxItems: 3
49    description:
50      Phandles to nvmem cell that contains the trimming data.
51      Available only for HS-PHY implemented on LD20 and PXs3, and
52      if unspecified, default value is used.
53
54  nvmem-cell-names:
55    items:
56      - const: rterm
57      - const: sel_t
58      - const: hs_i
59    description:
60      Should be the following names, which correspond to each nvmem-cells.
61      All of the 3 parameters associated with the above names are
62      required for each port, if any one is omitted, the trimming data
63      of the port will not be set at all.
64
65allOf:
66  - if:
67      properties:
68        compatible:
69          contains:
70            const: socionext,uniphier-pro5-usb3-hsphy
71    then:
72      properties:
73        clocks:
74          minItems: 2
75          maxItems: 2
76        clock-names:
77          items:
78            - const: gio
79            - const: link
80        resets:
81          minItems: 2
82          maxItems: 2
83        reset-names:
84          items:
85            - const: gio
86            - const: link
87  - if:
88      properties:
89        compatible:
90          contains:
91            enum:
92              - socionext,uniphier-pxs2-usb3-hsphy
93              - socionext,uniphier-ld20-usb3-hsphy
94    then:
95      properties:
96        clocks:
97          minItems: 2
98          maxItems: 2
99        clock-names:
100          items:
101            - const: link
102            - const: phy
103        resets:
104          minItems: 2
105          maxItems: 2
106        reset-names:
107          items:
108            - const: link
109            - const: phy
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - socionext,uniphier-pxs3-usb3-hsphy
116              - socionext,uniphier-nx1-usb3-hsphy
117    then:
118      properties:
119        clocks:
120          minItems: 2
121          maxItems: 3
122        clock-names:
123          minItems: 2
124          items:
125            - const: link
126            - const: phy
127            - const: phy-ext
128        resets:
129          minItems: 2
130          maxItems: 2
131        reset-names:
132          items:
133            - const: link
134            - const: phy
135
136required:
137  - compatible
138  - reg
139  - "#phy-cells"
140  - clocks
141  - clock-names
142  - resets
143  - reset-names
144
145additionalProperties: false
146
147examples:
148  - |
149    usb-glue@65b00000 {
150        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
151        #address-cells = <1>;
152        #size-cells = <1>;
153        ranges = <0 0x65b00000 0x400>;
154
155        usb_hsphy0: hs-phy@200 {
156            compatible = "socionext,uniphier-ld20-usb3-hsphy";
157            reg = <0x200 0x10>;
158            #phy-cells = <0>;
159            clock-names = "link", "phy";
160            clocks = <&sys_clk 14>, <&sys_clk 16>;
161            reset-names = "link", "phy";
162            resets = <&sys_rst 14>, <&sys_rst 16>;
163            vbus-supply = <&usb_vbus0>;
164            nvmem-cell-names = "rterm", "sel_t", "hs_i";
165            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
166        };
167    };
168