xref: /freebsd/sys/contrib/device-tree/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml (revision d30a1689f5b37e78ea189232a8b94a7011dc0dc8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9description: |
10  This describes the devicetree bindings for PHY interfaces built into
11  USB3 controller implemented on Socionext UniPhier SoCs.
12  Although the controller includes High-Speed PHY and Super-Speed PHY,
13  this describes about High-Speed PHY.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19  compatible:
20    enum:
21      - socionext,uniphier-pro5-usb3-hsphy
22      - socionext,uniphier-pxs2-usb3-hsphy
23      - socionext,uniphier-ld20-usb3-hsphy
24      - socionext,uniphier-pxs3-usb3-hsphy
25      - socionext,uniphier-nx1-usb3-hsphy
26
27  reg:
28    maxItems: 1
29
30  "#phy-cells":
31    const: 0
32
33  clocks:
34    minItems: 1
35    maxItems: 3
36
37  clock-names:
38    oneOf:
39      - const: link          # for PXs2
40      - items:               # for PXs3 with phy-ext
41          - const: link
42          - const: phy
43          - const: phy-ext
44      - items:               # for others
45          - const: link
46          - const: phy
47
48  resets:
49    maxItems: 2
50
51  reset-names:
52    items:
53      - const: link
54      - const: phy
55
56  vbus-supply:
57    description: A phandle to the regulator for USB VBUS
58
59  nvmem-cells:
60    maxItems: 3
61    description:
62      Phandles to nvmem cell that contains the trimming data.
63      Available only for HS-PHY implemented on LD20 and PXs3, and
64      if unspecified, default value is used.
65
66  nvmem-cell-names:
67    items:
68      - const: rterm
69      - const: sel_t
70      - const: hs_i
71    description:
72      Should be the following names, which correspond to each nvmem-cells.
73      All of the 3 parameters associated with the above names are
74      required for each port, if any one is omitted, the trimming data
75      of the port will not be set at all.
76
77required:
78  - compatible
79  - reg
80  - "#phy-cells"
81  - clocks
82  - clock-names
83  - resets
84  - reset-names
85
86additionalProperties: false
87
88examples:
89  - |
90    usb-glue@65b00000 {
91        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
92        #address-cells = <1>;
93        #size-cells = <1>;
94        ranges = <0 0x65b00000 0x400>;
95
96        usb_hsphy0: hs-phy@200 {
97            compatible = "socionext,uniphier-ld20-usb3-hsphy";
98            reg = <0x200 0x10>;
99            #phy-cells = <0>;
100            clock-names = "link", "phy";
101            clocks = <&sys_clk 14>, <&sys_clk 16>;
102            reset-names = "link", "phy";
103            resets = <&sys_rst 14>, <&sys_rst 16>;
104            vbus-supply = <&usb_vbus0>;
105            nvmem-cell-names = "rterm", "sel_t", "hs_i";
106            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
107        };
108    };
109