1Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY 2------------------------------------------------- 3 4Required properties: 5- compatible : should be one of the listed compatibles: 6 - "samsung,s5pv210-mipi-video-phy" 7 - "samsung,exynos5420-mipi-video-phy" 8 - "samsung,exynos5433-mipi-video-phy" 9- #phy-cells : from the generic phy bindings, must be 1; 10 11In case of s5pv210 and exynos5420 compatible PHYs: 12- syscon - phandle to the PMU system controller 13 14In case of exynos5433 compatible PHY: 15 - samsung,pmu-syscon - phandle to the PMU system controller 16 - samsung,disp-sysreg - phandle to the DISP system registers controller 17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller 18 - samsung,cam1-sysreg - phandle to the CAM1 system registers controller 19 20For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in 21the PHY specifier identifies the PHY and its meaning is as follows: 22 0 - MIPI CSIS 0, 23 1 - MIPI DSIM 0, 24 2 - MIPI CSIS 1, 25 3 - MIPI DSIM 1. 26"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy" 27supports additional fifth PHY: 28 4 - MIPI CSIS 2. 29 30Samsung Exynos SoC series Display Port PHY 31------------------------------------------------- 32 33Required properties: 34- compatible : should be one of the following supported values: 35 - "samsung,exynos5250-dp-video-phy" 36 - "samsung,exynos5420-dp-video-phy" 37- samsung,pmu-syscon: phandle for PMU system controller interface, used to 38 control pmu registers for power isolation. 39- #phy-cells : from the generic PHY bindings, must be 0; 40 41Samsung S5P/Exynos SoC series USB PHY 42------------------------------------------------- 43 44Required properties: 45- compatible : should be one of the listed compatibles: 46 - "samsung,exynos3250-usb2-phy" 47 - "samsung,exynos4210-usb2-phy" 48 - "samsung,exynos4x12-usb2-phy" 49 - "samsung,exynos5250-usb2-phy" 50 - "samsung,exynos5420-usb2-phy" 51 - "samsung,s5pv210-usb2-phy" 52- reg : a list of registers used by phy driver 53 - first and obligatory is the location of phy modules registers 54- samsung,sysreg-phandle - handle to syscon used to control the system registers 55- samsung,pmureg-phandle - handle to syscon used to control PMU registers 56- #phy-cells : from the generic phy bindings, must be 1; 57- clocks and clock-names: 58 - the "phy" clock is required by the phy module, used as a gate 59 - the "ref" clock is used to get the rate of the clock provided to the 60 PHY module 61 62Optional properties: 63- vbus-supply: power-supply phandle for vbus power source 64 65The first phandle argument in the PHY specifier identifies the PHY, its 66meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 67and Exynos 4212) it is as follows: 68 0 - USB device ("device"), 69 1 - USB host ("host"), 70 2 - HSIC0 ("hsic0"), 71 3 - HSIC1 ("hsic1"), 72Exynos3250 has only USB device phy available as phy 0. 73 74Exynos 4210 and Exynos 4212 use mode switching and require that mode switch 75register is supplied. 76 77Example: 78 79For Exynos 4412 (compatible with Exynos 4212): 80 81usbphy: phy@125b0000 { 82 compatible = "samsung,exynos4x12-usb2-phy"; 83 reg = <0x125b0000 0x100>; 84 clocks = <&clock 305>, <&clock 2>; 85 clock-names = "phy", "ref"; 86 #phy-cells = <1>; 87 samsung,sysreg-phandle = <&sys_reg>; 88 samsung,pmureg-phandle = <&pmu_reg>; 89}; 90 91Then the PHY can be used in other nodes such as: 92 93phy-consumer@12340000 { 94 phys = <&usbphy 2>; 95 phy-names = "phy"; 96}; 97 98Refer to DT bindings documentation of particular PHY consumer devices for more 99information about required PHYs and the way of specification. 100 101Samsung SATA PHY Controller 102--------------------------- 103 104SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. 105Each SATA PHY controller should have its own node. 106 107Required properties: 108- compatible : compatible list, contains "samsung,exynos5250-sata-phy" 109- reg : offset and length of the SATA PHY register set; 110- #phy-cells : must be zero 111- clocks : must be exactly one entry 112- clock-names : must be "sata_phyctrl" 113- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments 114- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments 115 116Example: 117 sata_phy: sata-phy@12170000 { 118 compatible = "samsung,exynos5250-sata-phy"; 119 reg = <0x12170000 0x1ff>; 120 clocks = <&clock 287>; 121 clock-names = "sata_phyctrl"; 122 #phy-cells = <0>; 123 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; 124 samsung,syscon-phandle = <&pmu_syscon>; 125 }; 126 127Device-Tree bindings for sataphy i2c client driver 128-------------------------------------------------- 129 130Required properties: 131compatible: Should be "samsung,exynos-sataphy-i2c" 132- reg: I2C address of the sataphy i2c device. 133 134Example: 135 136 sata_phy_i2c:sata-phy@38 { 137 compatible = "samsung,exynos-sataphy-i2c"; 138 reg = <0x38>; 139 }; 140 141Samsung Exynos5 SoC series USB DRD PHY controller 142-------------------------------------------------- 143 144Required properties: 145- compatible : Should be set to one of the following supported values: 146 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, 147 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. 148 - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. 149 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. 150- reg : Register offset and length of USB DRD PHY register set; 151- clocks: Clock IDs array as required by the controller 152- clock-names: names of clocks correseponding to IDs in the clock property; 153 Required clocks: 154 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), 155 used for register access. 156 - ref: PHY's reference clock (usually crystal clock), used for 157 PHY operations, associated by phy name. It is used to 158 determine bit values for clock settings register. 159 For Exynos5420 this is given as 'sclk_usbphy30' in CMU. 160 - optional clocks: Exynos5433 & Exynos7 SoC has now following additional 161 gate clocks available: 162 - phy_pipe: for PIPE3 phy 163 - phy_utmi: for UTMI+ phy 164 - itp: for ITP generation 165- samsung,pmu-syscon: phandle for PMU system controller interface, used to 166 control pmu registers for power isolation. 167- #phy-cells : from the generic PHY bindings, must be 1; 168 169For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy" 170compatible PHYs, the second cell in the PHY specifier identifies the 171PHY id, which is interpreted as follows: 172 0 - UTMI+ type phy, 173 1 - PIPE3 type phy, 174 175Example: 176 usbdrd_phy: usbphy@12100000 { 177 compatible = "samsung,exynos5250-usbdrd-phy"; 178 reg = <0x12100000 0x100>; 179 clocks = <&clock 286>, <&clock 1>; 180 clock-names = "phy", "ref"; 181 samsung,pmu-syscon = <&pmu_system_controller>; 182 #phy-cells = <1>; 183 }; 184 185- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, 186 'usbdrd_phy' nodes should have numbered alias in the aliases node, 187 in the form of usbdrdphyN, N = 0, 1... (depending on number of 188 controllers). 189Example: 190 aliases { 191 usbdrdphy0 = &usb3_phy0; 192 usbdrdphy1 = &usb3_phy1; 193 }; 194 195Samsung Exynos SoC series PCIe PHY controller 196-------------------------------------------------- 197Required properties: 198- compatible : Should be set to "samsung,exynos5440-pcie-phy" 199- #phy-cells : Must be zero 200- reg : a register used by phy driver. 201 - First is for phy register, second is for block register. 202- reg-names : Must be set to "phy" and "block". 203 204Example: 205 pcie_phy0: pcie-phy@270000 { 206 #phy-cells = <0>; 207 compatible = "samsung,exynos5440-pcie-phy"; 208 reg = <0x270000 0x1000>, <0x271000 0x40>; 209 reg-names = "phy", "block"; 210 }; 211