xref: /freebsd/sys/contrib/device-tree/Bindings/phy/samsung,usb3-drd-phy.yaml (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - samsung,exynos5250-usbdrd-phy
29      - samsung,exynos5420-usbdrd-phy
30      - samsung,exynos5433-usbdrd-phy
31      - samsung,exynos7-usbdrd-phy
32
33  clocks:
34    minItems: 2
35    maxItems: 5
36
37  clock-names:
38    minItems: 2
39    maxItems: 5
40    description: |
41      At least two clocks::
42        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
43          for register access.
44        - PHY reference clock (usually crystal clock), used for PHY operations,
45          associated by phy name. It is used to determine bit values for clock
46          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
47          in the CMU.
48
49  "#phy-cells":
50    const: 1
51
52  port:
53    $ref: /schemas/graph.yaml#/properties/port
54    description:
55      Any connector to the data bus of this controller should be modelled using
56      the OF graph bindings specified.
57
58  reg:
59    maxItems: 1
60
61  samsung,pmu-syscon:
62    $ref: /schemas/types.yaml#/definitions/phandle
63    description:
64      Phandle to PMU system controller interface.
65
66  vbus-supply:
67    description:
68      VBUS power source.
69
70  vbus-boost-supply:
71    description:
72      VBUS Boost 5V power source.
73
74required:
75  - compatible
76  - clocks
77  - clock-names
78  - "#phy-cells"
79  - reg
80  - samsung,pmu-syscon
81
82allOf:
83  - if:
84      properties:
85        compatible:
86          contains:
87            enum:
88              - samsung,exynos5433-usbdrd-phy
89              - samsung,exynos7-usbdrd-phy
90    then:
91      properties:
92        clocks:
93          minItems: 5
94          maxItems: 5
95        clock-names:
96          items:
97            - const: phy
98            - const: ref
99            - const: phy_utmi
100            - const: phy_pipe
101            - const: itp
102    else:
103      properties:
104        clocks:
105          minItems: 2
106          maxItems: 2
107        clock-names:
108          items:
109            - const: phy
110            - const: ref
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/clock/exynos5420.h>
117
118    phy@12100000 {
119        compatible = "samsung,exynos5420-usbdrd-phy";
120        reg = <0x12100000 0x100>;
121        #phy-cells = <1>;
122        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
123        clock-names = "phy", "ref";
124        samsung,pmu-syscon = <&pmu_system_controller>;
125        vbus-supply = <&usb300_vbus_reg>;
126    };
127