xref: /freebsd/sys/contrib/device-tree/Bindings/phy/samsung,ufs-phy.yaml (revision d8096b2df282d7a50e56eddba523bcdda1676106) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series UFS PHY Device Tree Bindings
8
9maintainers:
10  - Alim Akhtar <alim.akhtar@samsung.com>
11
12properties:
13  "#phy-cells":
14    const: 0
15
16  compatible:
17    enum:
18      - samsung,exynos7-ufs-phy
19      - samsung,exynosautov9-ufs-phy
20      - tesla,fsd-ufs-phy
21
22  reg:
23    maxItems: 1
24
25  reg-names:
26    items:
27      - const: phy-pma
28
29  clocks:
30    items:
31      - description: PLL reference clock
32      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
33      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
34      - description: symbol clock for output symbol ( tx0 symbol clock)
35
36  clock-names:
37    items:
38      - const: ref_clk
39      - const: rx1_symbol_clk
40      - const: rx0_symbol_clk
41      - const: tx0_symbol_clk
42
43  samsung,pmu-syscon:
44    $ref: '/schemas/types.yaml#/definitions/phandle-array'
45    maxItems: 1
46    items:
47      minItems: 1
48      items:
49        - description: phandle for PMU system controller interface, used to
50                       control pmu registers bits for ufs m-phy
51        - description: offset of the pmu control register
52    description:
53      It can be phandle/offset pair. The second cell which can represent an
54      offset is optional.
55
56required:
57  - "#phy-cells"
58  - compatible
59  - reg
60  - reg-names
61  - clocks
62  - clock-names
63  - samsung,pmu-syscon
64
65additionalProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/clock/exynos7-clk.h>
70
71    ufs_phy: ufs-phy@15571800 {
72        compatible = "samsung,exynos7-ufs-phy";
73        reg = <0x15571800 0x240>;
74        reg-names = "phy-pma";
75        samsung,pmu-syscon = <&pmu_system_controller>;
76        #phy-cells = <0>;
77        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
78                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
79                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
80                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
81        clock-names = "ref_clk", "rx1_symbol_clk",
82                      "rx0_symbol_clk", "tx0_symbol_clk";
83
84    };
85...
86