1# SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip SoC MIPI RX0 D-PHY 8 9maintainers: 10 - Helen Koike <helen.koike@collabora.com> 11 - Ezequiel Garcia <ezequiel@collabora.com> 12 13description: | 14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to 15 the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. 16 17properties: 18 compatible: 19 const: rockchip,rk3399-mipi-dphy-rx0 20 21 clocks: 22 items: 23 - description: MIPI D-PHY ref clock 24 - description: MIPI D-PHY RX0 cfg clock 25 - description: Video in/out general register file clock 26 27 clock-names: 28 items: 29 - const: dphy-ref 30 - const: dphy-cfg 31 - const: grf 32 33 '#phy-cells': 34 const: 0 35 36 power-domains: 37 description: Video in/out power domain. 38 maxItems: 1 39 40required: 41 - compatible 42 - clocks 43 - clock-names 44 - '#phy-cells' 45 - power-domains 46 47additionalProperties: false 48 49examples: 50 - | 51 52 /* 53 * MIPI D-PHY RX0 use registers in "general register files", it 54 * should be a child of the GRF. 55 * 56 * grf: syscon@ff770000 { 57 * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 58 * ... 59 * }; 60 */ 61 62 #include <dt-bindings/clock/rk3399-cru.h> 63 #include <dt-bindings/power/rk3399-power.h> 64 65 mipi_dphy_rx0: mipi-dphy-rx0 { 66 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 67 clocks = <&cru SCLK_MIPIDPHY_REF>, 68 <&cru SCLK_DPHY_RX0_CFG>, 69 <&cru PCLK_VIO_GRF>; 70 clock-names = "dphy-ref", "dphy-cfg", "grf"; 71 power-domains = <&power RK3399_PD_VIO>; 72 #phy-cells = <0>; 73 }; 74