1Qualcomm PCIe2 PHY controller 2============================= 3 4The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm 5platforms. 6 7Required properties: 8 - compatible: compatible list, should be: 9 "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" 10 11 - reg: offset and length of the PHY register set. 12 - #phy-cells: must be 0. 13 14 - clocks: a clock-specifier pair for the "pipe" clock 15 16 - vdda-vp-supply: phandle to low voltage regulator 17 - vdda-vph-supply: phandle to high voltage regulator 18 19 - resets: reset-specifier pairs for the "phy" and "pipe" resets 20 - reset-names: list of resets, should contain: 21 "phy" and "pipe" 22 23 - clock-output-names: name of the outgoing clock signal from the PHY PLL 24 - #clock-cells: must be 0 25 26Example: 27 phy@7786000 { 28 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 29 reg = <0x07786000 0xb8>; 30 31 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 32 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 33 <&gcc GCC_PCIE_0_PIPE_ARES>; 34 reset-names = "phy", "pipe"; 35 36 vdda-vp-supply = <&vreg_l3_1p05>; 37 vdda-vph-supply = <&vreg_l5_1p8>; 38 39 clock-output-names = "pcie_0_pipe_clk"; 40 #clock-cells = <0>; 41 #phy-cells = <0>; 42 }; 43