xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sar2130p-qmp-usb3-dp-phy
20      - qcom,sc7180-qmp-usb3-dp-phy
21      - qcom,sc7280-qmp-usb3-dp-phy
22      - qcom,sc8180x-qmp-usb3-dp-phy
23      - qcom,sc8280xp-qmp-usb43dp-phy
24      - qcom,sdm845-qmp-usb3-dp-phy
25      - qcom,sm6350-qmp-usb3-dp-phy
26      - qcom,sm8150-qmp-usb3-dp-phy
27      - qcom,sm8250-qmp-usb3-dp-phy
28      - qcom,sm8350-qmp-usb3-dp-phy
29      - qcom,sm8450-qmp-usb3-dp-phy
30      - qcom,sm8550-qmp-usb3-dp-phy
31      - qcom,sm8650-qmp-usb3-dp-phy
32      - qcom,sm8750-qmp-usb3-dp-phy
33      - qcom,x1e80100-qmp-usb3-dp-phy
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    minItems: 4
40    maxItems: 5
41
42  clock-names:
43    minItems: 4
44    items:
45      - const: aux
46      - const: ref
47      - const: com_aux
48      - const: usb3_pipe
49      - const: cfg_ahb
50
51  power-domains:
52    maxItems: 1
53
54  resets:
55    maxItems: 2
56
57  reset-names:
58    items:
59      - const: phy
60      - const: common
61
62  vdda-phy-supply: true
63
64  vdda-pll-supply: true
65
66  "#clock-cells":
67    const: 1
68    description:
69      See include/dt-bindings/phy/phy-qcom-qmp.h
70
71  "#phy-cells":
72    const: 1
73    description:
74      See include/dt-bindings/phy/phy-qcom-qmp.h
75
76  orientation-switch:
77    description:
78      Flag the PHY as possible handler of USB Type-C orientation switching
79    type: boolean
80
81  ports:
82    $ref: /schemas/graph.yaml#/properties/ports
83    properties:
84      port@0:
85        $ref: /schemas/graph.yaml#/properties/port
86        description: Output endpoint of the PHY
87
88      port@1:
89        $ref: /schemas/graph.yaml#/properties/port
90        description: Incoming endpoint from the USB controller
91
92      port@2:
93        $ref: /schemas/graph.yaml#/properties/port
94        description: Incoming endpoint from the DisplayPort controller
95
96required:
97  - compatible
98  - reg
99  - clocks
100  - clock-names
101  - resets
102  - reset-names
103  - vdda-phy-supply
104  - vdda-pll-supply
105  - "#clock-cells"
106  - "#phy-cells"
107
108allOf:
109  - if:
110      properties:
111        compatible:
112          enum:
113            - qcom,sc7180-qmp-usb3-dp-phy
114            - qcom,sdm845-qmp-usb3-dp-phy
115    then:
116      properties:
117        clocks:
118          maxItems: 5
119        clock-names:
120          maxItems: 5
121    else:
122      properties:
123        clocks:
124          maxItems: 4
125        clock-names:
126          maxItems: 4
127
128  - if:
129      properties:
130        compatible:
131          enum:
132            - qcom,sar2130p-qmp-usb3-dp-phy
133            - qcom,sc8280xp-qmp-usb43dp-phy
134            - qcom,sm6350-qmp-usb3-dp-phy
135            - qcom,sm8550-qmp-usb3-dp-phy
136            - qcom,sm8650-qmp-usb3-dp-phy
137            - qcom,sm8750-qmp-usb3-dp-phy
138            - qcom,x1e80100-qmp-usb3-dp-phy
139    then:
140      required:
141        - power-domains
142    else:
143      properties:
144        power-domains: false
145
146additionalProperties: false
147
148examples:
149  - |
150    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
151
152    phy@88eb000 {
153      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
154      reg = <0x088eb000 0x4000>;
155
156      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
157               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
158               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
159               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
160      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
161
162      power-domains = <&gcc USB30_PRIM_GDSC>;
163
164      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
165               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
166      reset-names = "phy", "common";
167
168      vdda-phy-supply = <&vreg_l9d>;
169      vdda-pll-supply = <&vreg_l4d>;
170
171      orientation-switch;
172
173      #clock-cells = <1>;
174      #phy-cells = <1>;
175
176      ports {
177          #address-cells = <1>;
178          #size-cells = <0>;
179
180          port@0 {
181              reg = <0>;
182
183              endpoint {
184                  remote-endpoint = <&typec_connector_ss>;
185              };
186          };
187
188          port@1 {
189              reg = <1>;
190
191              endpoint {
192                  remote-endpoint = <&dwc3_ss_out>;
193              };
194          };
195
196          port@2 {
197              reg = <2>;
198
199              endpoint {
200                  remote-endpoint = <&mdss_dp_out>;
201              };
202          };
203      };
204    };
205