xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
20      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
21      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
22      - qcom,sdx65-qmp-gen4x2-pcie-phy
23      - qcom,sm8350-qmp-gen3x1-pcie-phy
24      - qcom,sm8550-qmp-gen3x2-pcie-phy
25      - qcom,sm8550-qmp-gen4x2-pcie-phy
26
27  reg:
28    minItems: 1
29    maxItems: 2
30
31  clocks:
32    minItems: 5
33    maxItems: 6
34
35  clock-names:
36    minItems: 5
37    items:
38      - const: aux
39      - const: cfg_ahb
40      - const: ref
41      - const: rchng
42      - const: pipe
43      - const: pipediv2
44
45  power-domains:
46    maxItems: 1
47
48  resets:
49    minItems: 1
50    maxItems: 2
51
52  reset-names:
53    minItems: 1
54    items:
55      - const: phy
56      - const: phy_nocsr
57
58  vdda-phy-supply: true
59
60  vdda-pll-supply: true
61
62  vdda-qref-supply: true
63
64  qcom,4ln-config-sel:
65    description: PCIe 4-lane configuration
66    $ref: /schemas/types.yaml#/definitions/phandle-array
67    items:
68      - items:
69          - description: phandle of TCSR syscon
70          - description: offset of PCIe 4-lane configuration register
71          - description: offset of configuration bit for this PHY
72
73  "#clock-cells":
74    const: 0
75
76  clock-output-names:
77    maxItems: 1
78
79  "#phy-cells":
80    const: 0
81
82required:
83  - compatible
84  - reg
85  - clocks
86  - clock-names
87  - power-domains
88  - resets
89  - reset-names
90  - vdda-phy-supply
91  - vdda-pll-supply
92  - "#clock-cells"
93  - clock-output-names
94  - "#phy-cells"
95
96additionalProperties: false
97
98allOf:
99  - if:
100      properties:
101        compatible:
102          contains:
103            enum:
104              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
105    then:
106      properties:
107        reg:
108          items:
109            - description: port a
110            - description: port b
111      required:
112        - qcom,4ln-config-sel
113    else:
114      properties:
115        reg:
116          maxItems: 1
117
118  - if:
119      properties:
120        compatible:
121          contains:
122            enum:
123              - qcom,sm8350-qmp-gen3x1-pcie-phy
124              - qcom,sm8550-qmp-gen3x2-pcie-phy
125              - qcom,sm8550-qmp-gen4x2-pcie-phy
126    then:
127      properties:
128        clocks:
129          maxItems: 5
130        clock-names:
131          maxItems: 5
132    else:
133      properties:
134        clocks:
135          minItems: 6
136        clock-names:
137          minItems: 6
138
139  - if:
140      properties:
141        compatible:
142          contains:
143            enum:
144              - qcom,sm8550-qmp-gen4x2-pcie-phy
145    then:
146      properties:
147        resets:
148          minItems: 2
149        reset-names:
150          minItems: 2
151    else:
152      properties:
153        resets:
154          maxItems: 1
155        reset-names:
156          maxItems: 1
157
158examples:
159  - |
160    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
161
162    pcie2b_phy: phy@1c18000 {
163      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
164      reg = <0x01c18000 0x2000>;
165
166      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
167               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
168               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
169               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
170               <&gcc GCC_PCIE_2B_PIPE_CLK>,
171               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
172      clock-names = "aux", "cfg_ahb", "ref", "rchng",
173                    "pipe", "pipediv2";
174
175      power-domains = <&gcc PCIE_2B_GDSC>;
176
177      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
178      reset-names = "phy";
179
180      vdda-phy-supply = <&vreg_l6d>;
181      vdda-pll-supply = <&vreg_l4d>;
182
183      #clock-cells = <0>;
184      clock-output-names = "pcie_2b_pipe_clk";
185
186      #phy-cells = <0>;
187    };
188
189    pcie2a_phy: phy@1c24000 {
190      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
191      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
192
193      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
194               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
195               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
196               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
197               <&gcc GCC_PCIE_2A_PIPE_CLK>,
198               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
199      clock-names = "aux", "cfg_ahb", "ref", "rchng",
200                    "pipe", "pipediv2";
201
202      power-domains = <&gcc PCIE_2A_GDSC>;
203
204      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
205      reset-names = "phy";
206
207      vdda-phy-supply = <&vreg_l6d>;
208      vdda-pll-supply = <&vreg_l4d>;
209
210      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
211
212      #clock-cells = <0>;
213      clock-output-names = "pcie_2a_pipe_clk";
214
215      #phy-cells = <0>;
216    };
217