xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml (revision 3f0efe05432b1633991114ca4ca330102a561959) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QMP USB3 DP PHY controller (SC7180)
9
10description:
11  The QMP PHY controller supports physical layer functionality for a number of
12  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
13
14  Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
15  qcom,sc8280xp-qmp-usb43dp-phy.yaml.
16
17maintainers:
18  - Wesley Cheng <quic_wcheng@quicinc.com>
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - qcom,sc7180-qmp-usb3-dp-phy
25          - qcom,sc8180x-qmp-usb3-dp-phy
26          - qcom,sdm845-qmp-usb3-dp-phy
27          - qcom,sm8250-qmp-usb3-dp-phy
28      - items:
29          - enum:
30              - qcom,sc7280-qmp-usb3-dp-phy
31          - const: qcom,sm8250-qmp-usb3-dp-phy
32
33  reg:
34    items:
35      - description: Address and length of PHY's USB serdes block.
36      - description: Address and length of the DP_COM control block.
37      - description: Address and length of PHY's DP serdes block.
38
39  reg-names:
40    items:
41      - const: usb
42      - const: dp_com
43      - const: dp
44
45  "#address-cells":
46    enum: [ 1, 2 ]
47
48  "#size-cells":
49    enum: [ 1, 2 ]
50
51  ranges: true
52
53  clocks:
54    minItems: 3
55    maxItems: 4
56
57  clock-names:
58    minItems: 3
59    maxItems: 4
60
61  power-domains:
62    maxItems: 1
63
64  orientation-switch:
65    description: Flag the port as possible handler of orientation switching
66    type: boolean
67
68  resets:
69    items:
70      - description: reset of phy block.
71      - description: phy common block reset.
72
73  reset-names:
74    items:
75      - const: phy
76      - const: common
77
78  vdda-phy-supply:
79    description:
80      Phandle to a regulator supply to PHY core block.
81
82  vdda-pll-supply:
83    description:
84      Phandle to 1.8V regulator supply to PHY refclk pll block.
85
86  vddp-ref-clk-supply:
87    description:
88      Phandle to a regulator supply to any specific refclk pll block.
89
90# Required nodes:
91patternProperties:
92  "^usb3-phy@[0-9a-f]+$":
93    type: object
94    additionalProperties: false
95    description:
96      The USB3 PHY.
97
98    properties:
99      reg:
100        items:
101          - description: Address and length of TX.
102          - description: Address and length of RX.
103          - description: Address and length of PCS.
104          - description: Address and length of TX2.
105          - description: Address and length of RX2.
106          - description: Address and length of pcs_misc.
107
108      clocks:
109        items:
110          - description: pipe clock
111
112      clock-names:
113        deprecated: true
114        items:
115          - const: pipe0
116
117      clock-output-names:
118        items:
119          - const: usb3_phy_pipe_clk_src
120
121      '#clock-cells':
122        const: 0
123
124      '#phy-cells':
125        const: 0
126
127    required:
128      - reg
129      - clocks
130      - '#clock-cells'
131      - '#phy-cells'
132
133  "^dp-phy@[0-9a-f]+$":
134    type: object
135    additionalProperties: false
136    description:
137      The DP PHY.
138
139    properties:
140      reg:
141        items:
142          - description: Address and length of TX.
143          - description: Address and length of RX.
144          - description: Address and length of PCS.
145          - description: Address and length of TX2.
146          - description: Address and length of RX2.
147
148      '#clock-cells':
149        const: 1
150
151      '#phy-cells':
152        const: 0
153
154    required:
155      - reg
156      - '#clock-cells'
157      - '#phy-cells'
158
159required:
160  - compatible
161  - reg
162  - "#address-cells"
163  - "#size-cells"
164  - ranges
165  - clocks
166  - clock-names
167  - resets
168  - reset-names
169  - vdda-phy-supply
170  - vdda-pll-supply
171
172allOf:
173  - if:
174      properties:
175        compatible:
176          enum:
177            - qcom,sc7180-qmp-usb3-dp-phy
178            - qcom,sdm845-qmp-usb3-dp-phy
179    then:
180      properties:
181        clocks:
182          items:
183            - description: Phy aux clock
184            - description: Phy config clock
185            - description: 19.2 MHz ref clk
186            - description: Phy common block aux clock
187        clock-names:
188          items:
189            - const: aux
190            - const: cfg_ahb
191            - const: ref
192            - const: com_aux
193
194  - if:
195      properties:
196        compatible:
197          enum:
198            - qcom,sc8180x-qmp-usb3-dp-phy
199    then:
200      properties:
201        clocks:
202          items:
203            - description: Phy aux clock
204            - description: 19.2 MHz ref clk
205            - description: Phy common block aux clock
206        clock-names:
207          items:
208            - const: aux
209            - const: ref
210            - const: com_aux
211
212  - if:
213      properties:
214        compatible:
215          enum:
216            - qcom,sm8250-qmp-usb3-dp-phy
217    then:
218      properties:
219        clocks:
220          items:
221            - description: Phy aux clock
222            - description: Board XO source
223            - description: Phy common block aux clock
224        clock-names:
225          items:
226            - const: aux
227            - const: ref_clk_src
228            - const: com_aux
229
230additionalProperties: false
231
232examples:
233  - |
234    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
235    usb_1_qmpphy: phy-wrapper@88e9000 {
236        compatible = "qcom,sdm845-qmp-usb3-dp-phy";
237        reg = <0x088e9000 0x18c>,
238              <0x088e8000 0x10>,
239              <0x088ea000 0x40>;
240        reg-names = "usb", "dp_com", "dp";
241        #address-cells = <1>;
242        #size-cells = <1>;
243        ranges = <0x0 0x088e9000 0x2000>;
244
245        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
246                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
247                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
248                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
249        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
250
251        resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
252                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
253        reset-names = "phy", "common";
254
255        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
256        vdda-pll-supply = <&vdda_usb2_ss_core>;
257
258        orientation-switch;
259
260        usb3-phy@200 {
261            reg = <0x200 0x128>,
262                  <0x400 0x200>,
263                  <0xc00 0x218>,
264                  <0x600 0x128>,
265                  <0x800 0x200>,
266                  <0xa00 0x100>;
267            #clock-cells = <0>;
268            #phy-cells = <0>;
269            clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
270            clock-output-names = "usb3_phy_pipe_clk_src";
271        };
272
273        dp-phy@88ea200 {
274            reg = <0xa200 0x200>,
275                  <0xa400 0x200>,
276                  <0xaa00 0x200>,
277                  <0xa600 0x200>,
278                  <0xa800 0x200>;
279            #clock-cells = <1>;
280            #phy-cells = <0>;
281        };
282    };
283