xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,qusb2-phy.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq8074-qusb2-phy
22              - qcom,msm8953-qusb2-phy
23              - qcom,msm8996-qusb2-phy
24              - qcom,msm8998-qusb2-phy
25              - qcom,qcm2290-qusb2-phy
26              - qcom,sdm660-qusb2-phy
27              - qcom,ipq6018-qusb2-phy
28              - qcom,sm4250-qusb2-phy
29              - qcom,sm6115-qusb2-phy
30      - items:
31          - enum:
32              - qcom,sc7180-qusb2-phy
33              - qcom,sdm670-qusb2-phy
34              - qcom,sdm845-qusb2-phy
35              - qcom,sm6350-qusb2-phy
36          - const: qcom,qusb2-v2-phy
37  reg:
38    maxItems: 1
39
40  "#phy-cells":
41    const: 0
42
43  clocks:
44    minItems: 2
45    items:
46      - description: phy config clock
47      - description: 19.2 MHz ref clk
48      - description: phy interface clock (Optional)
49
50  clock-names:
51    minItems: 2
52    items:
53      - const: cfg_ahb
54      - const: ref
55      - const: iface
56
57  vdd-supply:
58    description:
59      Phandle to 0.9V regulator supply to PHY digital circuit.
60
61  vdda-pll-supply:
62    description:
63      Phandle to 1.8V regulator supply to PHY refclk pll block.
64
65  vdda-phy-dpdm-supply:
66    description:
67      Phandle to 3.1V regulator supply to Dp/Dm port signals.
68
69  resets:
70    maxItems: 1
71    description:
72      Phandle to reset to phy block.
73
74  nvmem-cells:
75    maxItems: 1
76    description:
77      Phandle to nvmem cell that contains 'HS Tx trim'
78      tuning parameter value for qusb2 phy.
79
80  qcom,tcsr-syscon:
81    description:
82      Phandle to TCSR syscon register region.
83    $ref: /schemas/types.yaml#/definitions/phandle
84
85  qcom,imp-res-offset-value:
86    description:
87      It is a 6 bit value that specifies offset to be
88      added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
89      tuning parameter that may vary for different boards of same SOC.
90    $ref: /schemas/types.yaml#/definitions/uint32
91    minimum: 0
92    maximum: 63
93    default: 0
94
95  qcom,bias-ctrl-value:
96    description:
97      It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
98      tuning parameter that may vary for different boards of same SOC.
99    $ref: /schemas/types.yaml#/definitions/uint32
100    minimum: 0
101    maximum: 63
102    default: 32
103
104  qcom,charge-ctrl-value:
105    description:
106      It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
107      tuning parameter that may vary for different boards of same SOC.
108    $ref: /schemas/types.yaml#/definitions/uint32
109    minimum: 0
110    maximum: 3
111    default: 0
112
113  qcom,hstx-trim-value:
114    description:
115      It is a 4 bit value that specifies tuning for HSTX
116      output current.
117      Possible range is - 15mA to 24mA (stepsize of 600 uA).
118      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
119    $ref: /schemas/types.yaml#/definitions/uint32
120    minimum: 0
121    maximum: 15
122    default: 3
123
124  qcom,preemphasis-level:
125    description:
126      It is a 2 bit value that specifies pre-emphasis level.
127      Possible range is 0 to 15% (stepsize of 5%).
128      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
129    $ref: /schemas/types.yaml#/definitions/uint32
130    minimum: 0
131    maximum: 3
132    default: 2
133
134  qcom,preemphasis-width:
135    description:
136      It is a 1 bit value that specifies how long the HSTX
137      pre-emphasis (specified using qcom,preemphasis-level) must be in
138      effect. Duration could be half-bit of full-bit.
139      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
140    $ref: /schemas/types.yaml#/definitions/uint32
141    minimum: 0
142    maximum: 1
143    default: 0
144
145  qcom,hsdisc-trim-value:
146    description:
147      It is a 2 bit value tuning parameter that control disconnect
148      threshold and may vary for different boards of same SOC.
149    $ref: /schemas/types.yaml#/definitions/uint32
150    minimum: 0
151    maximum: 3
152    default: 0
153
154required:
155  - compatible
156  - reg
157  - "#phy-cells"
158  - clocks
159  - clock-names
160  - vdd-supply
161  - vdda-pll-supply
162  - vdda-phy-dpdm-supply
163  - resets
164
165allOf:
166  - if:
167      not:
168        properties:
169          compatible:
170            contains:
171              const: qcom,qusb2-v2-phy
172    then:
173      properties:
174        qcom,imp-res-offset-value: false
175        qcom,bias-ctrl-value: false
176        qcom,charge-ctrl-value: false
177        qcom,hstx-trim-value: false
178        qcom,preemphasis-level: false
179        qcom,preemphasis-width: false
180        qcom,hsdisc-trim-value: false
181
182additionalProperties: false
183
184examples:
185  - |
186    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
187    hsusb_phy: phy@7411000 {
188        compatible = "qcom,msm8996-qusb2-phy";
189        reg = <0x7411000 0x180>;
190        #phy-cells = <0>;
191
192        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
193                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
194        clock-names = "cfg_ahb", "ref";
195
196        vdd-supply = <&pm8994_l28>;
197        vdda-pll-supply = <&pm8994_l12>;
198        vdda-phy-dpdm-supply = <&pm8994_l24>;
199
200        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
201        nvmem-cells = <&qusb2p_hstx_trim>;
202    };
203