xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,qusb2-phy.yaml (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq6018-qusb2-phy
22              - qcom,ipq8074-qusb2-phy
23              - qcom,ipq9574-qusb2-phy
24              - qcom,msm8953-qusb2-phy
25              - qcom,msm8996-qusb2-phy
26              - qcom,msm8998-qusb2-phy
27              - qcom,qcm2290-qusb2-phy
28              - qcom,sdm660-qusb2-phy
29              - qcom,sm4250-qusb2-phy
30              - qcom,sm6115-qusb2-phy
31      - items:
32          - enum:
33              - qcom,sc7180-qusb2-phy
34              - qcom,sdm670-qusb2-phy
35              - qcom,sdm845-qusb2-phy
36              - qcom,sm6350-qusb2-phy
37          - const: qcom,qusb2-v2-phy
38  reg:
39    maxItems: 1
40
41  "#phy-cells":
42    const: 0
43
44  clocks:
45    minItems: 2
46    items:
47      - description: phy config clock
48      - description: 19.2 MHz ref clk
49      - description: phy interface clock (Optional)
50
51  clock-names:
52    minItems: 2
53    items:
54      - const: cfg_ahb
55      - const: ref
56      - const: iface
57
58  vdd-supply:
59    description:
60      Phandle to 0.9V regulator supply to PHY digital circuit.
61
62  vdda-pll-supply:
63    description:
64      Phandle to 1.8V regulator supply to PHY refclk pll block.
65
66  vdda-phy-dpdm-supply:
67    description:
68      Phandle to 3.1V regulator supply to Dp/Dm port signals.
69
70  resets:
71    maxItems: 1
72    description:
73      Phandle to reset to phy block.
74
75  nvmem-cells:
76    maxItems: 1
77    description:
78      Phandle to nvmem cell that contains 'HS Tx trim'
79      tuning parameter value for qusb2 phy.
80
81  qcom,tcsr-syscon:
82    description:
83      Phandle to TCSR syscon register region.
84    $ref: /schemas/types.yaml#/definitions/phandle
85
86  qcom,imp-res-offset-value:
87    description:
88      It is a 6 bit value that specifies offset to be
89      added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
90      tuning parameter that may vary for different boards of same SOC.
91    $ref: /schemas/types.yaml#/definitions/uint32
92    minimum: 0
93    maximum: 63
94    default: 0
95
96  qcom,bias-ctrl-value:
97    description:
98      It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
99      tuning parameter that may vary for different boards of same SOC.
100    $ref: /schemas/types.yaml#/definitions/uint32
101    minimum: 0
102    maximum: 63
103    default: 32
104
105  qcom,charge-ctrl-value:
106    description:
107      It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
108      tuning parameter that may vary for different boards of same SOC.
109    $ref: /schemas/types.yaml#/definitions/uint32
110    minimum: 0
111    maximum: 3
112    default: 0
113
114  qcom,hstx-trim-value:
115    description:
116      It is a 4 bit value that specifies tuning for HSTX
117      output current.
118      Possible range is - 15mA to 24mA (stepsize of 600 uA).
119      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
120    $ref: /schemas/types.yaml#/definitions/uint32
121    minimum: 0
122    maximum: 15
123    default: 3
124
125  qcom,preemphasis-level:
126    description:
127      It is a 2 bit value that specifies pre-emphasis level.
128      Possible range is 0 to 15% (stepsize of 5%).
129      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
130    $ref: /schemas/types.yaml#/definitions/uint32
131    minimum: 0
132    maximum: 3
133    default: 2
134
135  qcom,preemphasis-width:
136    description:
137      It is a 1 bit value that specifies how long the HSTX
138      pre-emphasis (specified using qcom,preemphasis-level) must be in
139      effect. Duration could be half-bit of full-bit.
140      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
141    $ref: /schemas/types.yaml#/definitions/uint32
142    minimum: 0
143    maximum: 1
144    default: 0
145
146  qcom,hsdisc-trim-value:
147    description:
148      It is a 2 bit value tuning parameter that control disconnect
149      threshold and may vary for different boards of same SOC.
150    $ref: /schemas/types.yaml#/definitions/uint32
151    minimum: 0
152    maximum: 3
153    default: 0
154
155required:
156  - compatible
157  - reg
158  - "#phy-cells"
159  - clocks
160  - clock-names
161  - vdd-supply
162  - vdda-pll-supply
163  - vdda-phy-dpdm-supply
164  - resets
165
166allOf:
167  - if:
168      not:
169        properties:
170          compatible:
171            contains:
172              const: qcom,qusb2-v2-phy
173    then:
174      properties:
175        qcom,imp-res-offset-value: false
176        qcom,bias-ctrl-value: false
177        qcom,charge-ctrl-value: false
178        qcom,hstx-trim-value: false
179        qcom,preemphasis-level: false
180        qcom,preemphasis-width: false
181        qcom,hsdisc-trim-value: false
182
183additionalProperties: false
184
185examples:
186  - |
187    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
188    hsusb_phy: phy@7411000 {
189        compatible = "qcom,msm8996-qusb2-phy";
190        reg = <0x7411000 0x180>;
191        #phy-cells = <0>;
192
193        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
194                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
195        clock-names = "cfg_ahb", "ref";
196
197        vdd-supply = <&pm8994_l28>;
198        vdda-pll-supply = <&pm8994_l12>;
199        vdda-phy-dpdm-supply = <&pm8994_l24>;
200
201        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
202        nvmem-cells = <&qusb2p_hstx_trim>;
203    };
204