xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,qusb2-phy.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq8074-qusb2-phy
22              - qcom,msm8953-qusb2-phy
23              - qcom,msm8996-qusb2-phy
24              - qcom,msm8998-qusb2-phy
25              - qcom,qcm2290-qusb2-phy
26              - qcom,sdm660-qusb2-phy
27              - qcom,ipq6018-qusb2-phy
28              - qcom,sm4250-qusb2-phy
29              - qcom,sm6115-qusb2-phy
30      - items:
31          - enum:
32              - qcom,sc7180-qusb2-phy
33              - qcom,sdm845-qusb2-phy
34              - qcom,sm6350-qusb2-phy
35          - const: qcom,qusb2-v2-phy
36  reg:
37    maxItems: 1
38
39  "#phy-cells":
40    const: 0
41
42  clocks:
43    minItems: 2
44    items:
45      - description: phy config clock
46      - description: 19.2 MHz ref clk
47      - description: phy interface clock (Optional)
48
49  clock-names:
50    minItems: 2
51    items:
52      - const: cfg_ahb
53      - const: ref
54      - const: iface
55
56  vdd-supply:
57    description:
58      Phandle to 0.9V regulator supply to PHY digital circuit.
59
60  vdda-pll-supply:
61    description:
62      Phandle to 1.8V regulator supply to PHY refclk pll block.
63
64  vdda-phy-dpdm-supply:
65    description:
66      Phandle to 3.1V regulator supply to Dp/Dm port signals.
67
68  resets:
69    maxItems: 1
70    description:
71      Phandle to reset to phy block.
72
73  nvmem-cells:
74    maxItems: 1
75    description:
76      Phandle to nvmem cell that contains 'HS Tx trim'
77      tuning parameter value for qusb2 phy.
78
79  qcom,tcsr-syscon:
80    description:
81      Phandle to TCSR syscon register region.
82    $ref: /schemas/types.yaml#/definitions/phandle
83
84if:
85  properties:
86    compatible:
87      contains:
88        const: qcom,qusb2-v2-phy
89then:
90  properties:
91    qcom,imp-res-offset-value:
92      description:
93        It is a 6 bit value that specifies offset to be
94        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
95        tuning parameter that may vary for different boards of same SOC.
96      $ref: /schemas/types.yaml#/definitions/uint32
97      minimum: 0
98      maximum: 63
99      default: 0
100
101    qcom,bias-ctrl-value:
102      description:
103        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
104        tuning parameter that may vary for different boards of same SOC.
105      $ref: /schemas/types.yaml#/definitions/uint32
106      minimum: 0
107      maximum: 63
108      default: 32
109
110    qcom,charge-ctrl-value:
111      description:
112        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
113        tuning parameter that may vary for different boards of same SOC.
114      $ref: /schemas/types.yaml#/definitions/uint32
115      minimum: 0
116      maximum: 3
117      default: 0
118
119    qcom,hstx-trim-value:
120      description:
121        It is a 4 bit value that specifies tuning for HSTX
122        output current.
123        Possible range is - 15mA to 24mA (stepsize of 600 uA).
124        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
125      $ref: /schemas/types.yaml#/definitions/uint32
126      minimum: 0
127      maximum: 15
128      default: 3
129
130    qcom,preemphasis-level:
131      description:
132        It is a 2 bit value that specifies pre-emphasis level.
133        Possible range is 0 to 15% (stepsize of 5%).
134        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
135      $ref: /schemas/types.yaml#/definitions/uint32
136      minimum: 0
137      maximum: 3
138      default: 2
139
140    qcom,preemphasis-width:
141      description:
142        It is a 1 bit value that specifies how long the HSTX
143        pre-emphasis (specified using qcom,preemphasis-level) must be in
144        effect. Duration could be half-bit of full-bit.
145        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
146      $ref: /schemas/types.yaml#/definitions/uint32
147      minimum: 0
148      maximum: 1
149      default: 0
150
151    qcom,hsdisc-trim-value:
152      description:
153        It is a 2 bit value tuning parameter that control disconnect
154        threshold and may vary for different boards of same SOC.
155      $ref: /schemas/types.yaml#/definitions/uint32
156      minimum: 0
157      maximum: 3
158      default: 0
159
160required:
161  - compatible
162  - reg
163  - "#phy-cells"
164  - clocks
165  - clock-names
166  - vdd-supply
167  - vdda-pll-supply
168  - vdda-phy-dpdm-supply
169  - resets
170
171additionalProperties: false
172
173examples:
174  - |
175    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
176    hsusb_phy: phy@7411000 {
177        compatible = "qcom,msm8996-qusb2-phy";
178        reg = <0x7411000 0x180>;
179        #phy-cells = <0>;
180
181        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
182                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
183        clock-names = "cfg_ahb", "ref";
184
185        vdd-supply = <&pm8994_l28>;
186        vdda-pll-supply = <&pm8994_l12>;
187        vdda-phy-dpdm-supply = <&pm8994_l24>;
188
189        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
190        nvmem-cells = <&qusb2p_hstx_trim>;
191    };
192