xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QMP USB3 DP PHY controller
9
10maintainers:
11  - Manu Gautam <mgautam@codeaurora.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,sc7180-qmp-usb3-phy
17      - qcom,sdm845-qmp-usb3-phy
18  reg:
19    items:
20      - description: Address and length of PHY's common serdes block.
21      - description: Address and length of the DP_COM control block.
22
23  reg-names:
24    items:
25      - const: reg-base
26      - const: dp_com
27
28  "#clock-cells":
29    enum: [ 1, 2 ]
30
31  "#address-cells":
32    enum: [ 1, 2 ]
33
34  "#size-cells":
35    enum: [ 1, 2 ]
36
37  ranges: true
38
39  clocks:
40    items:
41      - description: Phy aux clock.
42      - description: Phy config clock.
43      - description: 19.2 MHz ref clk.
44      - description: Phy common block aux clock.
45
46  clock-names:
47    items:
48      - const: aux
49      - const: cfg_ahb
50      - const: ref
51      - const: com_aux
52
53  resets:
54    items:
55      - description: reset of phy block.
56      - description: phy common block reset.
57
58  reset-names:
59    items:
60      - const: phy
61      - const: common
62
63  vdda-phy-supply:
64    description:
65      Phandle to a regulator supply to PHY core block.
66
67  vdda-pll-supply:
68    description:
69      Phandle to 1.8V regulator supply to PHY refclk pll block.
70
71  vddp-ref-clk-supply:
72    description:
73      Phandle to a regulator supply to any specific refclk pll block.
74
75#Required nodes:
76patternProperties:
77  "^phy@[0-9a-f]+$":
78    type: object
79    description:
80      Each device node of QMP phy is required to have as many child nodes as
81      the number of lanes the PHY has.
82
83required:
84  - compatible
85  - reg
86  - reg-names
87  - "#clock-cells"
88  - "#address-cells"
89  - "#size-cells"
90  - ranges
91  - clocks
92  - clock-names
93  - resets
94  - reset-names
95  - vdda-phy-supply
96  - vdda-pll-supply
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
103    usb_1_qmpphy: phy-wrapper@88e9000 {
104        compatible = "qcom,sdm845-qmp-usb3-phy";
105        reg = <0x088e9000 0x18c>,
106              <0x088e8000 0x10>;
107        reg-names = "reg-base", "dp_com";
108        #clock-cells = <1>;
109        #address-cells = <1>;
110        #size-cells = <1>;
111        ranges = <0x0 0x088e9000 0x1000>;
112
113        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
114                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
115                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
116                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
117        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
118
119        resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
120                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
121        reset-names = "phy", "common";
122
123        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
124        vdda-pll-supply = <&vdda_usb2_ss_core>;
125
126        phy@200 {
127            reg = <0x200 0x128>,
128                  <0x400 0x200>,
129                  <0xc00 0x218>,
130                  <0x600 0x128>,
131                  <0x800 0x200>,
132                  <0xa00 0x100>;
133            #clock-cells = <0>;
134            #phy-cells = <0>;
135            clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
136            clock-names = "pipe0";
137            clock-output-names = "usb3_phy_pipe_clk_src";
138        };
139    };
140