xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml (revision 1d386b48a555f61cb7325543adbbb5c3f3407a66) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QMP USB3 DP PHY controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13properties:
14  compatible:
15    enum:
16      - qcom,sc7180-qmp-usb3-dp-phy
17      - qcom,sc7280-qmp-usb3-dp-phy
18      - qcom,sc8180x-qmp-usb3-dp-phy
19      - qcom,sc8280xp-qmp-usb43dp-phy
20      - qcom,sdm845-qmp-usb3-dp-phy
21      - qcom,sm8250-qmp-usb3-dp-phy
22  reg:
23    items:
24      - description: Address and length of PHY's USB serdes block.
25      - description: Address and length of the DP_COM control block.
26      - description: Address and length of PHY's DP serdes block.
27
28  reg-names:
29    items:
30      - const: usb
31      - const: dp_com
32      - const: dp
33
34  "#address-cells":
35    enum: [ 1, 2 ]
36
37  "#size-cells":
38    enum: [ 1, 2 ]
39
40  ranges: true
41
42  clocks:
43    items:
44      - description: Phy aux clock.
45      - description: Phy config clock.
46      - description: 19.2 MHz ref clk.
47      - description: Phy common block aux clock.
48
49  clock-names:
50    items:
51      - const: aux
52      - const: cfg_ahb
53      - const: ref
54      - const: com_aux
55
56  power-domains:
57    maxItems: 1
58
59  resets:
60    items:
61      - description: reset of phy block.
62      - description: phy common block reset.
63
64  reset-names:
65    items:
66      - const: phy
67      - const: common
68
69  vdda-phy-supply:
70    description:
71      Phandle to a regulator supply to PHY core block.
72
73  vdda-pll-supply:
74    description:
75      Phandle to 1.8V regulator supply to PHY refclk pll block.
76
77  vddp-ref-clk-supply:
78    description:
79      Phandle to a regulator supply to any specific refclk pll block.
80
81#Required nodes:
82patternProperties:
83  "^usb3-phy@[0-9a-f]+$":
84    type: object
85    additionalProperties: false
86    description:
87      The USB3 PHY.
88
89    properties:
90      reg:
91        items:
92          - description: Address and length of TX.
93          - description: Address and length of RX.
94          - description: Address and length of PCS.
95          - description: Address and length of TX2.
96          - description: Address and length of RX2.
97          - description: Address and length of pcs_misc.
98
99      clocks:
100        items:
101          - description: pipe clock
102
103      clock-names:
104        deprecated: true
105        items:
106          - const: pipe0
107
108      clock-output-names:
109        items:
110          - const: usb3_phy_pipe_clk_src
111
112      '#clock-cells':
113        const: 0
114
115      '#phy-cells':
116        const: 0
117
118    required:
119      - reg
120      - clocks
121      - '#clock-cells'
122      - '#phy-cells'
123
124  "^dp-phy@[0-9a-f]+$":
125    type: object
126    additionalProperties: false
127    description:
128      The DP PHY.
129
130    properties:
131      reg:
132        items:
133          - description: Address and length of TX.
134          - description: Address and length of RX.
135          - description: Address and length of PCS.
136          - description: Address and length of TX2.
137          - description: Address and length of RX2.
138
139      '#clock-cells':
140        const: 1
141
142      '#phy-cells':
143        const: 0
144
145    required:
146      - reg
147      - '#clock-cells'
148      - '#phy-cells'
149
150required:
151  - compatible
152  - reg
153  - "#address-cells"
154  - "#size-cells"
155  - ranges
156  - clocks
157  - clock-names
158  - resets
159  - reset-names
160  - vdda-phy-supply
161  - vdda-pll-supply
162
163additionalProperties: false
164
165allOf:
166  - if:
167      properties:
168        compatible:
169          contains:
170            enum:
171              - qcom,sc8280xp-qmp-usb43dp-phy
172    then:
173      required:
174        - power-domains
175
176examples:
177  - |
178    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
179    usb_1_qmpphy: phy-wrapper@88e9000 {
180        compatible = "qcom,sdm845-qmp-usb3-dp-phy";
181        reg = <0x088e9000 0x18c>,
182              <0x088e8000 0x10>,
183              <0x088ea000 0x40>;
184        reg-names = "usb", "dp_com", "dp";
185        #address-cells = <1>;
186        #size-cells = <1>;
187        ranges = <0x0 0x088e9000 0x2000>;
188
189        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
190                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
191                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
192                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
193        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
194
195        resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
196                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
197        reset-names = "phy", "common";
198
199        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
200        vdda-pll-supply = <&vdda_usb2_ss_core>;
201
202        usb3-phy@200 {
203            reg = <0x200 0x128>,
204                  <0x400 0x200>,
205                  <0xc00 0x218>,
206                  <0x600 0x128>,
207                  <0x800 0x200>,
208                  <0xa00 0x100>;
209            #clock-cells = <0>;
210            #phy-cells = <0>;
211            clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
212            clock-output-names = "usb3_phy_pipe_clk_src";
213        };
214
215        dp-phy@88ea200 {
216            reg = <0xa200 0x200>,
217                  <0xa400 0x200>,
218                  <0xaa00 0x200>,
219                  <0xa600 0x200>,
220                  <0xa800 0x200>;
221            #clock-cells = <1>;
222            #phy-cells = <0>;
223        };
224    };
225