1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Qualcomm QMP PHY controller 9 10maintainers: 11 - Vinod Koul <vkoul@kernel.org> 12 13description: 14 QMP phy controller supports physical layer functionality for a number of 15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 16 17properties: 18 compatible: 19 enum: 20 - qcom,ipq6018-qmp-pcie-phy 21 - qcom,ipq6018-qmp-usb3-phy 22 - qcom,ipq8074-qmp-pcie-phy 23 - qcom,ipq8074-qmp-usb3-phy 24 - qcom,msm8996-qmp-pcie-phy 25 - qcom,msm8996-qmp-ufs-phy 26 - qcom,msm8996-qmp-usb3-phy 27 - qcom,msm8998-qmp-pcie-phy 28 - qcom,msm8998-qmp-ufs-phy 29 - qcom,msm8998-qmp-usb3-phy 30 - qcom,qcm2290-qmp-usb3-phy 31 - qcom,sc7180-qmp-usb3-phy 32 - qcom,sc8180x-qmp-pcie-phy 33 - qcom,sc8180x-qmp-ufs-phy 34 - qcom,sc8180x-qmp-usb3-phy 35 - qcom,sc8280xp-qmp-ufs-phy 36 - qcom,sdm845-qhp-pcie-phy 37 - qcom,sdm845-qmp-pcie-phy 38 - qcom,sdm845-qmp-ufs-phy 39 - qcom,sdm845-qmp-usb3-phy 40 - qcom,sdm845-qmp-usb3-uni-phy 41 - qcom,sm6115-qmp-ufs-phy 42 - qcom,sm8150-qmp-ufs-phy 43 - qcom,sm8150-qmp-usb3-phy 44 - qcom,sm8150-qmp-usb3-uni-phy 45 - qcom,sm8250-qmp-ufs-phy 46 - qcom,sm8250-qmp-gen3x1-pcie-phy 47 - qcom,sm8250-qmp-gen3x2-pcie-phy 48 - qcom,sm8250-qmp-modem-pcie-phy 49 - qcom,sm8250-qmp-usb3-phy 50 - qcom,sm8250-qmp-usb3-uni-phy 51 - qcom,sm8350-qmp-ufs-phy 52 - qcom,sm8350-qmp-usb3-phy 53 - qcom,sm8350-qmp-usb3-uni-phy 54 - qcom,sm8450-qmp-gen3x1-pcie-phy 55 - qcom,sm8450-qmp-gen4x2-pcie-phy 56 - qcom,sm8450-qmp-ufs-phy 57 - qcom,sm8450-qmp-usb3-phy 58 - qcom,sdx55-qmp-pcie-phy 59 - qcom,sdx55-qmp-usb3-uni-phy 60 61 reg: 62 minItems: 1 63 items: 64 - description: Address and length of PHY's common serdes block. 65 - description: Address and length of PHY's DP_COM control block. 66 67 "#clock-cells": 68 enum: [ 1, 2 ] 69 70 "#address-cells": 71 enum: [ 1, 2 ] 72 73 "#size-cells": 74 enum: [ 1, 2 ] 75 76 ranges: true 77 78 clocks: 79 minItems: 1 80 maxItems: 4 81 82 clock-names: 83 minItems: 1 84 maxItems: 4 85 86 resets: 87 minItems: 1 88 maxItems: 3 89 90 reset-names: 91 minItems: 1 92 maxItems: 3 93 94 vdda-phy-supply: 95 description: 96 Phandle to a regulator supply to PHY core block. 97 98 vdda-pll-supply: 99 description: 100 Phandle to 1.8V regulator supply to PHY refclk pll block. 101 102 vddp-ref-clk-supply: 103 description: 104 Phandle to a regulator supply to any specific refclk pll block. 105 106#Required nodes: 107patternProperties: 108 "^phy@[0-9a-f]+$": 109 type: object 110 description: 111 Each device node of QMP phy is required to have as many child nodes as 112 the number of lanes the PHY has. 113 114required: 115 - compatible 116 - reg 117 - "#clock-cells" 118 - "#address-cells" 119 - "#size-cells" 120 - ranges 121 - clocks 122 - clock-names 123 - resets 124 - reset-names 125 126additionalProperties: false 127 128allOf: 129 - if: 130 properties: 131 compatible: 132 contains: 133 enum: 134 - qcom,sdm845-qmp-usb3-uni-phy 135 then: 136 properties: 137 clocks: 138 items: 139 - description: Phy aux clock. 140 - description: Phy config clock. 141 - description: 19.2 MHz ref clk. 142 - description: Phy common block aux clock. 143 clock-names: 144 items: 145 - const: aux 146 - const: cfg_ahb 147 - const: ref 148 - const: com_aux 149 resets: 150 items: 151 - description: reset of phy block. 152 - description: phy common block reset. 153 reset-names: 154 items: 155 - const: phy 156 - const: common 157 required: 158 - vdda-phy-supply 159 - vdda-pll-supply 160 - if: 161 properties: 162 compatible: 163 contains: 164 enum: 165 - qcom,sdx55-qmp-usb3-uni-phy 166 then: 167 properties: 168 clocks: 169 items: 170 - description: Phy aux clock. 171 - description: Phy config clock. 172 - description: 19.2 MHz ref clk. 173 clock-names: 174 items: 175 - const: aux 176 - const: cfg_ahb 177 - const: ref 178 resets: 179 items: 180 - description: reset of phy block. 181 - description: phy common block reset. 182 reset-names: 183 items: 184 - const: phy 185 - const: common 186 required: 187 - vdda-phy-supply 188 - vdda-pll-supply 189 - if: 190 properties: 191 compatible: 192 contains: 193 enum: 194 - qcom,msm8996-qmp-pcie-phy 195 then: 196 properties: 197 clocks: 198 items: 199 - description: Phy aux clock. 200 - description: Phy config clock. 201 - description: 19.2 MHz ref clk. 202 clock-names: 203 items: 204 - const: aux 205 - const: cfg_ahb 206 - const: ref 207 resets: 208 items: 209 - description: reset of phy block. 210 - description: phy common block reset. 211 - description: phy's ahb cfg block reset. 212 reset-names: 213 items: 214 - const: phy 215 - const: common 216 - const: cfg 217 required: 218 - vdda-phy-supply 219 - vdda-pll-supply 220 - if: 221 properties: 222 compatible: 223 contains: 224 enum: 225 - qcom,ipq8074-qmp-usb3-phy 226 - qcom,msm8996-qmp-usb3-phy 227 - qcom,msm8998-qmp-pcie-phy 228 - qcom,msm8998-qmp-usb3-phy 229 then: 230 properties: 231 clocks: 232 items: 233 - description: Phy aux clock. 234 - description: Phy config clock. 235 - description: 19.2 MHz ref clk. 236 clock-names: 237 items: 238 - const: aux 239 - const: cfg_ahb 240 - const: ref 241 resets: 242 items: 243 - description: reset of phy block. 244 - description: phy common block reset. 245 reset-names: 246 items: 247 - const: phy 248 - const: common 249 required: 250 - vdda-phy-supply 251 - vdda-pll-supply 252 - if: 253 properties: 254 compatible: 255 contains: 256 enum: 257 - qcom,msm8996-qmp-ufs-phy 258 then: 259 properties: 260 clocks: 261 items: 262 - description: 19.2 MHz ref clk. 263 clock-names: 264 items: 265 - const: ref 266 resets: 267 items: 268 - description: PHY reset in the UFS controller. 269 reset-names: 270 items: 271 - const: ufsphy 272 required: 273 - vdda-phy-supply 274 - vdda-pll-supply 275 - if: 276 properties: 277 compatible: 278 contains: 279 enum: 280 - qcom,msm8998-qmp-ufs-phy 281 - qcom,sdm845-qmp-ufs-phy 282 - qcom,sm8150-qmp-ufs-phy 283 - qcom,sm8250-qmp-ufs-phy 284 - qcom,sc8180x-qmp-ufs-phy 285 - qcom,sc8280xp-qmp-ufs-phy 286 then: 287 properties: 288 clocks: 289 items: 290 - description: 19.2 MHz ref clk. 291 - description: Phy reference aux clock. 292 clock-names: 293 items: 294 - const: ref 295 - const: ref_aux 296 resets: 297 items: 298 - description: PHY reset in the UFS controller. 299 reset-names: 300 items: 301 - const: ufsphy 302 required: 303 - vdda-phy-supply 304 - vdda-pll-supply 305 - if: 306 properties: 307 compatible: 308 contains: 309 enum: 310 - qcom,ipq6018-qmp-pcie-phy 311 - qcom,ipq8074-qmp-pcie-phy 312 then: 313 properties: 314 clocks: 315 items: 316 - description: Phy aux clock. 317 - description: Phy config clock. 318 clock-names: 319 items: 320 - const: aux 321 - const: cfg_ahb 322 resets: 323 items: 324 - description: reset of phy block. 325 - description: phy common block reset. 326 reset-names: 327 items: 328 - const: phy 329 - const: common 330 - if: 331 properties: 332 compatible: 333 contains: 334 enum: 335 - qcom,sc8180x-qmp-pcie-phy 336 - qcom,sdm845-qhp-pcie-phy 337 - qcom,sdm845-qmp-pcie-phy 338 - qcom,sdx55-qmp-pcie-phy 339 - qcom,sm8250-qmp-gen3x1-pcie-phy 340 - qcom,sm8250-qmp-gen3x2-pcie-phy 341 - qcom,sm8250-qmp-modem-pcie-phy 342 - qcom,sm8450-qmp-gen3x1-pcie-phy 343 - qcom,sm8450-qmp-gen4x2-pcie-phy 344 then: 345 properties: 346 clocks: 347 items: 348 - description: Phy aux clock. 349 - description: Phy config clock. 350 - description: 19.2 MHz ref clk. 351 - description: Phy refgen clk. 352 clock-names: 353 items: 354 - const: aux 355 - const: cfg_ahb 356 - const: ref 357 - const: refgen 358 resets: 359 items: 360 - description: reset of phy block. 361 reset-names: 362 items: 363 - const: phy 364 required: 365 - vdda-phy-supply 366 - vdda-pll-supply 367 - if: 368 properties: 369 compatible: 370 contains: 371 enum: 372 - qcom,sm8150-qmp-usb3-phy 373 - qcom,sm8150-qmp-usb3-uni-phy 374 - qcom,sm8250-qmp-usb3-uni-phy 375 - qcom,sm8350-qmp-usb3-uni-phy 376 then: 377 properties: 378 clocks: 379 items: 380 - description: Phy aux clock. 381 - description: 19.2 MHz ref clk source. 382 - description: 19.2 MHz ref clk. 383 - description: Phy common block aux clock. 384 clock-names: 385 items: 386 - const: aux 387 - const: ref_clk_src 388 - const: ref 389 - const: com_aux 390 resets: 391 items: 392 - description: reset of phy block. 393 - description: phy common block reset. 394 reset-names: 395 items: 396 - const: phy 397 - const: common 398 required: 399 - vdda-phy-supply 400 - vdda-pll-supply 401 - if: 402 properties: 403 compatible: 404 contains: 405 enum: 406 - qcom,sm8250-qmp-usb3-phy 407 - qcom,sm8350-qmp-usb3-phy 408 then: 409 properties: 410 clocks: 411 items: 412 - description: Phy aux clock. 413 - description: 19.2 MHz ref clk. 414 - description: Phy common block aux clock. 415 clock-names: 416 items: 417 - const: aux 418 - const: ref_clk_src 419 - const: com_aux 420 resets: 421 items: 422 - description: reset of phy block. 423 - description: phy common block reset. 424 reset-names: 425 items: 426 - const: phy 427 - const: common 428 required: 429 - vdda-phy-supply 430 - vdda-pll-supply 431 - if: 432 properties: 433 compatible: 434 contains: 435 enum: 436 - qcom,qcm2290-qmp-usb3-phy 437 then: 438 properties: 439 clocks: 440 items: 441 - description: Phy config clock. 442 - description: 19.2 MHz ref clk. 443 - description: Phy common block aux clock. 444 clock-names: 445 items: 446 - const: cfg_ahb 447 - const: ref 448 - const: com_aux 449 resets: 450 items: 451 - description: phy_phy reset. 452 - description: reset of phy block. 453 reset-names: 454 items: 455 - const: phy_phy 456 - const: phy 457 required: 458 - vdda-phy-supply 459 - vdda-pll-supply 460 461examples: 462 - | 463 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 464 usb_2_qmpphy: phy-wrapper@88eb000 { 465 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 466 reg = <0x088eb000 0x18c>; 467 #clock-cells = <1>; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0x0 0x088eb000 0x2000>; 471 472 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, 473 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 474 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 475 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 476 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 477 478 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 479 <&gcc GCC_USB3_PHY_SEC_BCR>; 480 reset-names = "phy", "common"; 481 482 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 483 vdda-pll-supply = <&vdda_usb2_ss_core>; 484 485 usb_2_ssphy: phy@200 { 486 reg = <0x200 0x128>, 487 <0x400 0x1fc>, 488 <0x800 0x218>, 489 <0x600 0x70>; 490 #clock-cells = <0>; 491 #phy-cells = <0>; 492 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 493 clock-names = "pipe0"; 494 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 495 }; 496 }; 497