1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Qualcomm QMP PHY controller 9 10maintainers: 11 - Manu Gautam <mgautam@codeaurora.org> 12 13description: 14 QMP phy controller supports physical layer functionality for a number of 15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 16 17properties: 18 compatible: 19 enum: 20 - qcom,ipq8074-qmp-pcie-phy 21 - qcom,ipq8074-qmp-usb3-phy 22 - qcom,msm8996-qmp-pcie-phy 23 - qcom,msm8996-qmp-ufs-phy 24 - qcom,msm8996-qmp-usb3-phy 25 - qcom,msm8998-qmp-pcie-phy 26 - qcom,msm8998-qmp-ufs-phy 27 - qcom,msm8998-qmp-usb3-phy 28 - qcom,sc7180-qmp-usb3-phy 29 - qcom,sc8180x-qmp-ufs-phy 30 - qcom,sc8180x-qmp-usb3-phy 31 - qcom,sdm845-qhp-pcie-phy 32 - qcom,sdm845-qmp-pcie-phy 33 - qcom,sdm845-qmp-ufs-phy 34 - qcom,sdm845-qmp-usb3-phy 35 - qcom,sdm845-qmp-usb3-uni-phy 36 - qcom,sm8150-qmp-ufs-phy 37 - qcom,sm8150-qmp-usb3-phy 38 - qcom,sm8150-qmp-usb3-uni-phy 39 - qcom,sm8250-qmp-ufs-phy 40 - qcom,sm8250-qmp-gen3x1-pcie-phy 41 - qcom,sm8250-qmp-gen3x2-pcie-phy 42 - qcom,sm8250-qmp-modem-pcie-phy 43 - qcom,sm8250-qmp-usb3-phy 44 - qcom,sm8250-qmp-usb3-uni-phy 45 - qcom,sm8350-qmp-ufs-phy 46 - qcom,sm8350-qmp-usb3-phy 47 - qcom,sm8350-qmp-usb3-uni-phy 48 - qcom,sdx55-qmp-usb3-uni-phy 49 50 reg: 51 minItems: 1 52 maxItems: 2 53 items: 54 - description: Address and length of PHY's common serdes block. 55 - description: Address and length of PHY's DP_COM control block. 56 57 "#clock-cells": 58 enum: [ 1, 2 ] 59 60 "#address-cells": 61 enum: [ 1, 2 ] 62 63 "#size-cells": 64 enum: [ 1, 2 ] 65 66 ranges: true 67 68 clocks: 69 minItems: 1 70 maxItems: 4 71 72 clock-names: 73 minItems: 1 74 maxItems: 4 75 76 resets: 77 minItems: 1 78 maxItems: 3 79 80 reset-names: 81 minItems: 1 82 maxItems: 3 83 84 vdda-phy-supply: 85 description: 86 Phandle to a regulator supply to PHY core block. 87 88 vdda-pll-supply: 89 description: 90 Phandle to 1.8V regulator supply to PHY refclk pll block. 91 92 vddp-ref-clk-supply: 93 description: 94 Phandle to a regulator supply to any specific refclk pll block. 95 96#Required nodes: 97patternProperties: 98 "^phy@[0-9a-f]+$": 99 type: object 100 description: 101 Each device node of QMP phy is required to have as many child nodes as 102 the number of lanes the PHY has. 103 104required: 105 - compatible 106 - reg 107 - "#clock-cells" 108 - "#address-cells" 109 - "#size-cells" 110 - ranges 111 - clocks 112 - clock-names 113 - resets 114 - reset-names 115 - vdda-phy-supply 116 - vdda-pll-supply 117 118additionalProperties: false 119 120allOf: 121 - if: 122 properties: 123 compatible: 124 contains: 125 enum: 126 - qcom,sdm845-qmp-usb3-uni-phy 127 then: 128 properties: 129 clocks: 130 items: 131 - description: Phy aux clock. 132 - description: Phy config clock. 133 - description: 19.2 MHz ref clk. 134 - description: Phy common block aux clock. 135 clock-names: 136 items: 137 - const: aux 138 - const: cfg_ahb 139 - const: ref 140 - const: com_aux 141 resets: 142 items: 143 - description: reset of phy block. 144 - description: phy common block reset. 145 reset-names: 146 items: 147 - const: phy 148 - const: common 149 - if: 150 properties: 151 compatible: 152 contains: 153 enum: 154 - qcom,sdx55-qmp-usb3-uni-phy 155 then: 156 properties: 157 clocks: 158 items: 159 - description: Phy aux clock. 160 - description: Phy config clock. 161 - description: 19.2 MHz ref clk. 162 clock-names: 163 items: 164 - const: aux 165 - const: cfg_ahb 166 - const: ref 167 resets: 168 items: 169 - description: reset of phy block. 170 - description: phy common block reset. 171 reset-names: 172 items: 173 - const: phy 174 - const: common 175 - if: 176 properties: 177 compatible: 178 contains: 179 enum: 180 - qcom,msm8996-qmp-pcie-phy 181 then: 182 properties: 183 clocks: 184 items: 185 - description: Phy aux clock. 186 - description: Phy config clock. 187 - description: 19.2 MHz ref clk. 188 clock-names: 189 items: 190 - const: aux 191 - const: cfg_ahb 192 - const: ref 193 resets: 194 items: 195 - description: reset of phy block. 196 - description: phy common block reset. 197 - description: phy's ahb cfg block reset. 198 reset-names: 199 items: 200 - const: phy 201 - const: common 202 - const: cfg 203 - if: 204 properties: 205 compatible: 206 contains: 207 enum: 208 - qcom,ipq8074-qmp-usb3-phy 209 - qcom,msm8996-qmp-usb3-phy 210 - qcom,msm8998-qmp-pcie-phy 211 - qcom,msm8998-qmp-usb3-phy 212 then: 213 properties: 214 clocks: 215 items: 216 - description: Phy aux clock. 217 - description: Phy config clock. 218 - description: 19.2 MHz ref clk. 219 clock-names: 220 items: 221 - const: aux 222 - const: cfg_ahb 223 - const: ref 224 resets: 225 items: 226 - description: reset of phy block. 227 - description: phy common block reset. 228 reset-names: 229 items: 230 - const: phy 231 - const: common 232 - if: 233 properties: 234 compatible: 235 contains: 236 enum: 237 - qcom,msm8996-qmp-ufs-phy 238 then: 239 properties: 240 clocks: 241 items: 242 - description: 19.2 MHz ref clk. 243 clock-names: 244 items: 245 - const: ref 246 resets: 247 items: 248 - description: PHY reset in the UFS controller. 249 reset-names: 250 items: 251 - const: ufsphy 252 - if: 253 properties: 254 compatible: 255 contains: 256 enum: 257 - qcom,msm8998-qmp-ufs-phy 258 - qcom,sdm845-qmp-ufs-phy 259 - qcom,sm8150-qmp-ufs-phy 260 - qcom,sm8250-qmp-ufs-phy 261 then: 262 properties: 263 clocks: 264 items: 265 - description: 19.2 MHz ref clk. 266 - description: Phy reference aux clock. 267 clock-names: 268 items: 269 - const: ref 270 - const: ref_aux 271 resets: 272 items: 273 - description: PHY reset in the UFS controller. 274 reset-names: 275 items: 276 - const: ufsphy 277 - if: 278 properties: 279 compatible: 280 contains: 281 enum: 282 - qcom,ipq8074-qmp-pcie-phy 283 then: 284 properties: 285 clocks: 286 items: 287 - description: pipe clk. 288 clock-names: 289 items: 290 - const: pipe_clk 291 resets: 292 items: 293 - description: reset of phy block. 294 - description: phy common block reset. 295 reset-names: 296 items: 297 - const: phy 298 - const: common 299 - if: 300 properties: 301 compatible: 302 contains: 303 enum: 304 - qcom,sdm845-qhp-pcie-phy 305 - qcom,sdm845-qmp-pcie-phy 306 - qcom,sm8250-qmp-gen3x1-pcie-phy 307 - qcom,sm8250-qmp-gen3x2-pcie-phy 308 - qcom,sm8250-qmp-modem-pcie-phy 309 then: 310 properties: 311 clocks: 312 items: 313 - description: Phy aux clock. 314 - description: Phy config clock. 315 - description: 19.2 MHz ref clk. 316 - description: Phy refgen clk. 317 clock-names: 318 items: 319 - const: aux 320 - const: cfg_ahb 321 - const: ref 322 - const: refgen 323 resets: 324 items: 325 - description: reset of phy block. 326 reset-names: 327 items: 328 - const: phy 329 - if: 330 properties: 331 compatible: 332 contains: 333 enum: 334 - qcom,sm8150-qmp-usb3-phy 335 - qcom,sm8150-qmp-usb3-uni-phy 336 - qcom,sm8250-qmp-usb3-uni-phy 337 - qcom,sm8350-qmp-usb3-uni-phy 338 then: 339 properties: 340 clocks: 341 items: 342 - description: Phy aux clock. 343 - description: 19.2 MHz ref clk source. 344 - description: 19.2 MHz ref clk. 345 - description: Phy common block aux clock. 346 clock-names: 347 items: 348 - const: aux 349 - const: ref_clk_src 350 - const: ref 351 - const: com_aux 352 resets: 353 items: 354 - description: reset of phy block. 355 - description: phy common block reset. 356 reset-names: 357 items: 358 - const: phy 359 - const: common 360 - if: 361 properties: 362 compatible: 363 contains: 364 enum: 365 - qcom,sm8250-qmp-usb3-phy 366 - qcom,sm8350-qmp-usb3-phy 367 then: 368 properties: 369 clocks: 370 items: 371 - description: Phy aux clock. 372 - description: 19.2 MHz ref clk. 373 - description: Phy common block aux clock. 374 clock-names: 375 items: 376 - const: aux 377 - const: ref_clk_src 378 - const: com_aux 379 resets: 380 items: 381 - description: reset of phy block. 382 - description: phy common block reset. 383 reset-names: 384 items: 385 - const: phy 386 - const: common 387 388examples: 389 - | 390 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 391 usb_2_qmpphy: phy-wrapper@88eb000 { 392 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 393 reg = <0x088eb000 0x18c>; 394 #clock-cells = <1>; 395 #address-cells = <1>; 396 #size-cells = <1>; 397 ranges = <0x0 0x088eb000 0x2000>; 398 399 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, 400 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 401 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 402 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 403 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 404 405 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 406 <&gcc GCC_USB3_PHY_SEC_BCR>; 407 reset-names = "phy", "common"; 408 409 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 410 vdda-pll-supply = <&vdda_usb2_ss_core>; 411 412 usb_2_ssphy: phy@200 { 413 reg = <0x200 0x128>, 414 <0x400 0x1fc>, 415 <0x800 0x218>, 416 <0x600 0x70>; 417 #clock-cells = <0>; 418 #phy-cells = <0>; 419 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 420 clock-names = "pipe0"; 421 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 422 }; 423 }; 424